AK8160B2 Datasheet, PDF (11/16 Pages) Asahi Kasei Microsystems – Low Power & Low Jitter Clock Generator for PCI Express

[AK8160B2]
PCIE0/1p
Vcross_median +75mV
Vcross_median
Vcross_median -75mV
Tr
Tf
PCIE0/1n
T_{slew_delta} (%) = 100 * 2 * (Tr - Tf) / (Tr + Tf)
Figure 7. Definition of Time Matching of Output Rising and Falling
Tperiod
Thigh
0.0V
Differential (PCIE0/1p)-(PCIE0/1n)
T_outdc (%) = 100 * Thigh / Tperiod
Figure 8. Definition of Output Duty Cycle
Vrb_max=100mV
Vrb_min=-100mV
Ring Back
Prohibited Ring Back Voltage Range
Differential (PCIE0/1p)-(PCIE0/1n)
Figure 9. Definition of Output Ring Back Voltage Margin
Ring Back
014003469-E-00
- 11 -
2014/06