AK4205EN Datasheet, PDF (11/25 Pages) Asahi Kasei Microsystems – Ultra Low Noise and Distortion Headphone Amp with Analog Switch

[AK4205]
■ DC Characteristics
(Ta = -40 ~ 85 C; PVDDA = PVDDB = RVDD = 4.5 V ~ 6.5 V, PVEEA = PVEEB = -4.5 V ~ -5.5 V,
SWVDD = 3.0 V ~ 3.6 V; AVSSA = AVSSB = RVSS = SWVSS = 0 V)
Parameter
Symbol Min.
Typ.
Max.
Unit
SEL, MUTEN, RSTN pins
High-Level Input Voltage
Low-Level Input Voltage
Input Rising Time
Input Falling Time
VIH
1.44
-
-
V
VIL
-
-
0.36
V
Tr
20
ns
Tf
20
ns
Input Leakage Current
Iin
-
-
0.5
μA
Output Voltage Hi-Fi Mode (SEL pin = “H”)
(CAPSS pin) AUX Mode (SEL pin = “L”)
2.37
2.5
2.63
V
1.3
1.4
1.5
V
■ Switching Characteristics
(Ta = -40 ~ 85 C; PVDDA = PVDDB = RVDD = 4.5 V ~ 6.5 V, PVEEA = PVEEB = -4.5 V ~ -5.5 V,
SWVDD = 3.0 V ~ 3.6 V; AVSSA = AVSSB = RVSS = SWVSS = 0 V)
Parameter (Figure 7)
Symbol Min.
Typ.
Max.
Unit
Soft Start Timing (RL=32Ω,Css=0.1μF: Note 33)
Turn-on Time
tON
59
ms
Turn-off Time
tOFF
29
ms
Turn-on slope (Vin = 20 mV)
tslON
1.0
V/s
Turn-off slope (offset Vin = 20 mV)
tslOFF
1.0
V/s
Reset Timing (RSTN pin: Note 33)
RSTN Pulse Width (Css = 0.1 μF)
tRST
2
-
-
ms
Note 33. Css is a capacitor connected with the CAPSS pin.
■ Headphone-amp Power-up/down Timing
Parameter (Figure 9)
Symbol Min.
Typ.
Max.
Unit
VDD Power up Slope (Note 34)
PUSLDD
-
-
15
mV/μs
VEE Power up Slope (Note 35)
PUSLEE -50
-
-
mV/μs
VDD Power down Slope (Note 34, Note 36) PDSLDD -100
-
-
mV/μs
VEE Power down Slope (Note 35, Note 36) PDSLEE
-
-
260 mV/μs
VDD-VEE non-overlap Time
tPU
0
-
-
ms
VEE-VDD non-overlap Time
tPD
0
-
-
ms
Note 34. RVDD, PVDDA, PVDDB pins
Note 35. PVEEA, PVEEB pins
Note 36. At power down, set the absolute value of the voltages of RVDD, PVDDA and PVDDB so that
they do not fall below the absolute value of the voltage of PVEEA and PVEEB.
016012367-E-00
- 11 -
2016/12