AK4186 Datasheet, PDF (11/33 Pages) Asahi Kasei Microsystems – Low Power Touch Screen Controller with I2C Interface

[AK4186]
■ Digital I/F
The AK4186 is controlled by a microprocessor via I²C bus and supports standard mode (100kHz) and fast mode
(400kHz). Note that the AK4186 operates in those two modes and does not support a High speed mode I²C-bus system
(3.4MHz). The AK4186 can operate as a slave device on the I²C bus network. The AK4186 operates off of supply
voltage down to 1.6V in order to connect a low voltage microprocessor.
4/5-wire touch panel
VDD=1.6V ~ 3.6V
AK4186
CAD0
Rp
Rp
“L” or “H”
SCL
SDA
PENIRQN
Micro-
Processor
I²C bus
Controller
Figure 6. Digital I/F
1. WRITE Operations
Figure 7 shows the data transfer sequence for the I²C-bus mode. All commands are preceded by START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 11). After the
START condition, a slave address is sent. This address is 6 bits long followed by the eighth bit that is a data direction
bit (R/W). The most significant five bits of the slave address are fixed as “100100”. The next bit is CAD0 (device
address bit). This bit identify the specific device on the bus. The hard-wired input pin (CAD0 pin) set this device
address bit (Figure 8). If the slave address matches that of the AK4186, the AK4186 generates an acknowledge and the
operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH)
during the acknowledge clock pulse (Figure 12). R/W bit value of “1” indicates that the read operation is to be executed.
“0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4186. The format is MSB first, and those most
significant two bits are fixed to zeros (Figure 9). The data after the second byte contains control data. The format is
MSB first, 8bits (Figure 10). The AK4186 generates an acknowledge after each byte is received. A data transfer is
always terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines STOP condition (Figure 11).
The AK4186 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4186
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating
the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter
is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1FH prior to
generating stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 13) except for the START and STOP conditions.
MS1068-E-04
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2011/03