AK4616VQ Datasheet, PDF (10/46 Pages) Asahi Kasei Microsystems – 24bit 3ch/5ch Audio CODEC with Mic Amplifier

[AK4616]
スイッチング特性
(Ta=-40∼+85°C; A3V31, A3V32= D3V3=3.0∼ 3.6V; D1V8=1.7∼ 1.9V; C_L=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Unit
Master Clock Timing
External Clock
256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
512fs:
Pulse Width Low
Pulse Width High
LRCK Timing (Slave mode)
Stereo mode
(TDM bit = “0”)
LRCK frequency
Duty Cycle
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
2.048
32
32
3.072
22
22
4.096
16
16
fs
8
Duty
45
12.288
18.432
24.576
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
48
kHz
55
%
TDM256 mode
(TDM bit = “1”)
LRCK frequency
“H” time
“L” time
Audio Interface Timing (Slave mode)
Stereo mode (TDM bit = “0”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
(Note 12)
BICK “↑” to LRCK Edge
(Note 12)
LRCK to SDTO(MSB) (Except I²S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
fs
tLRH
tLRL
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
8
1/256fs
1/256fs
324
130
130
20
20
50
50
48
kHz
ns
ns
ns
ns
ns
ns
ns
80
ns
80
ns
ns
ns
TDM256 mode
(TDM bit = “1”)
BICK Period
tBCK
81
ns
BICK Pulse Width Low
tBCKL
33
ns
Pulse Width High
tBCKH
33
ns
LRCK Edge to BICK “↑”
(Note 12) tLRB
23
ns
BICK “↑” to LRCK Edge
(Note 12) tBLR
23
ns
SDTO Setup time BICK “↑”
tBSS
6
ns
SDTO Hold time BICK “↑”
tBSH
5
ns
SDTI Hold Time
tSDH
10
ns
SDTI Setup Time
tSDS
10
ns
Note 12. この規格値はLRCKのエッジとBICKの “↑” が重ならないように規定しています。
MS1437-J-01
- 10 -
2012/11