AIC1574 Datasheet, PDF (17/20 Pages) Analog Intergrations Corporation – 5-bit DAC, Synchronous PWM Power Regulator with Triple Linear Controllers

current capability is to parallel several capaci-
tors. In most case, multiple electrolytic capaci-
tors of small case size are better than a single
large case capacitor.
Output Inductor Selection
Inductor value and type should be chosen based
on output slew rate requirement, output ripple
requirement and expected peak current. Induc-
tor value is primarily controlled by the required
current response time. The AIC1570 will provide
either 0% or 100% duty cycle in response to a
load transient. The response time to a transient
is different for the application of load and remove
of load.
tRISE = ^{L × ∆IOUT} tFALL = ^{L × ∆IOUT}
VIN − VOUT _,
VOUT _.
Where ^∆IOUT is transient load current step.
In a typical 5V input, 2V output application, a
3µH inductor has a 1A/µS rise time, resulting in
a 5µS delay in responding to a 5A load current
step. To optimize performance, different combi-
nations of input and output voltage and expected
loads may require different inductor value. A
smaller value of inductor will improve the tran-
sient response at the expense of increase out-
put ripple voltage and inductor core saturation
rating.
Peak current in the inductor will be equal to the
maximum output load current plus half of induc-
tor ripple current. The ripple current is approxi-
mately equal to:
IRIPPLE = ^{(VIN − VOUT) × VOUT}
f × L × VIN _;
f = AIC1574 oscillator frequency.
The inductor must be able to withstand peak
AIC1574
current without saturation, and the copper resis-
tance in the winding should be kept as low as
possible to minimize resistive power loss
Input Capacitor Selection
Most of the input supply current is supplied by
the input bypass capacitor, the resulting RMS
current flow in the input capacitor will heat it up.
Use a mix of input bulk capacitors to control the
voltage overshoot across the upper MOSFET.
The ceramic capacitance for the high frequency
decoupling should be placed very close to the
upper MOSFET to suppress the voltage induced
in the parasitic circuit impedance. The buck ca-
pacitors to supply the RMS current is approxi-
mate equal to:
IRMS = (1− D) ×
D×
I² OUT
+
1
12
×

VfIN_××LD
2
D = ^VOUT
, where
VIN
The capacitor voltage rating should be at least
1.25 times greater than the maximum input volt-
age.
PWM MOSFET Selection
In high current PWM application, the MOSFET
power dissipation, package type and heatsink
are the dominant design factors. The conduction
loss is the only component of power dissipation
for the lower MOSFET, since it turns on into
near zero voltage. The upper MOSFET has con-
duction loss and switching loss. The gate char-
ge losses are proportional to the switching fre-
quency and are dissipated by the AIC1574.
However, the gate charge increases the switch-
ing interval, t_SW, which increase the upper MOS-
FET switching losses. Ensure that both MOS-
FETs are within their maximum junction tem-
17