AIC1574 Datasheet, PDF(13/20 Page) Analog Intergrations Corporation – 5-bit DAC, Synchronous PWM Power Regulator with Triple Linear Controllers

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AIC1574 Datasheet, PDF (13/20 Pages) Analog Intergrations Corporation – 5-bit DAC, Synchronous PWM Power Regulator with Triple Linear Controllers

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AIC1574

extreme overload. A sustained overload on any output

or over-voltage on PWM output disable all converters

and drive the FAULT/RT pin to VCC.

LUV

OC1

0.15V

4.0V

OVER CURRENT

LATCH

INHIBIT

COUNTER

POR

FAULT LATCH

VCC

FAULT

Fig. 17 Simplified Schematic of Fault Logic

A simplified schematic is shown in figure 17. An

over-voltage detected on VSEN1 immediately sets

the fault latch. A sequence of three over-current

fault signals also sets the fault latch. An under-

voltage event on either linear output (VSEN2,

VSEN3, VSEN4) is ignored until the soft-start inter-

val. Cycling the bias input voltage (+12V off then on)

resets the counter and the fault latch.

Gate Drive Overlap Protection

The Overlap Protection circuit ensures that the Bot-

tom MOSFET does not turn on until the Upper

MOSFET source has reached a voltage low enough

to ensure that shoot-through will not occur.

A separate over-voltage circuit provides protection

during the initial application of power. For voltage on

VCC pin below the power-on reset (and above ~4V),

should VSEN1 exceed 1.0V, the lower MOSFET

(Q2) is driven on as needed to regulate VOUT1 to

1.0V.

Over-Current Protection

All outputs are protected against excessive over-

current. The PWM controller uses upper

MOSFETâs on-resistance, RDS(ON) to monitor the

current for protection against shorted outputs. All

linear controllers monitor VSEN for under-voltage

events to protect against excessive current.

Over-Voltage Protection

During operation, a short on the upper PWM

MOSFET (Q1) causes VOUT1 to increase. When

the output exceed the over-voltage threshold of

116% of DACOUT, the FAULT pin is set to fault

latch and turns Q2 on as required in order to regu-

late VOUT1 to 115% of DACOUT. The fault latch

raises the FAULT/RT pin close to VCC potential.

When the voltage across Q1 (ID RDS(ON)) exceeds

the level (200ÂµA ROCSET), this signal inhibit all

outputs. Discharge soft-start capacitor (Css) with

25ÂµA current sink, and increments the counter.

Css recharges and initiates a soft-start cycle again

until the counter increments to 3. This sets the fault

latch to disable all outputs. Fig. 6 illustrates the

over-current protection until an over load on OUT1.

Should excessive current cause VSEN to fall below

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