AIC1384 Datasheet, PDF (10/15 Pages) Analog Intergrations Corporation – DDR Termination Regulator

AIC1384
APPLICATION INFORMATION
The AIC1384 linear termination regulator is
designed to meet JEDEC requirements of DDR-
SDRAM (DDRŗ/Ř). The V_TT is able to deliver
sinking and sourcing current while regulating the
voltage equal to VDDQ/2. The output stage
includes a sense function to maintain excellent
load regulation to prevent shoot through. The
power part has two distinct rails that split the
internal analog circuitry from power output stage,
which results in reducing internal power
disspation.
Series Stub Termination Logic (SSTL) was
created to improve signal integrity of the data
transmission across the memory bus. This
termination scheme is necessary to prevent data
error from signal reflections while transmitting at
high frequencies encountered with DDR-SDRAM.
The achievement of single parallel termination
can be seen as below figure.
VIN VTT
ChipSet
RT _Memory
RS _VREF
Between the chipset and memory are one RS
series resistor and one RT termination resistor.
Both RS and RT are 25 Ohms typically; they can
be altered to scale the current requirements from
the AIC1384.
AVIN and PVIN
AVIN and PVIN have the ability to work with
separate supplies depending on the application.
Higher PVIN will increase the maximum
continuous output current resulting from output
R_DS-ON limitations at voltages close to V_TT.
Oppositely, the internal power dissipation will also
increase at high PVIN. Connect AVIN and PVIN
together with 2.5V is a good compromise in
SSTL-2 applications. This reduces the need for
bypassing two supply pins separately. For the
safe operation of the system; AVIN must always
exceed or equal to PVIN.
VDDQ
VDDQ is used to make internal reference voltage
for regulating V_TT. And V_TT will track VDDQ/2
precisely because of internal resistor divider. For
SSTL-2 application, connect VDDQ to the 2.5V
rail directly at the DIMM instead of AVIN and
PVIN to achieve that reference voltage tracks the
DDR memory rails accurately without a voltage
drop from power lines.
V_SENSE
The sense pin is used to improve remote load
regulation. The termination resistors in most
motherboards connect to V_TT with a long trace
that will cause a significant voltage drop. The
V_SENSE pin can improve that a lower termination
voltage at one end of the bus than the other by
connecting it to the middle of the bus. If a long
V_SENSE trace is implemented close to the memory,
noise pickup can be a problem in precise
regulation of V_TT. A small 0.1µF ceramic capacitor
can be used for filtering noise. V_SENSE pin must
still tie to V_TT if remote load regulation is not used.
V_REF
V_REF provides the buffered output of the internal
VDDQ/2 reference voltage. It can be used to
support the reference voltage for the Northbridge
chipset and memory. The V_REF remains active
during the shutdown state and thermal shutdown
for the Suspend to RAM functionality. A bypass
capacitor, located close to the V_REF pin, can be
used to improve performance. Ranging from
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