DSP1620 Datasheet, PDF (42/114 Pages) Agere Systems – Clarification to the Serial I/O Control Register Description for the DSP1620/27/28/29 Devices

DSP1628 Digital Signal Processor
4 Hardware Architecture (continued)
XTLOFF
OFF
CKI2
SMALL SIGNAL
CLOCK
CKI
MASK-PROGRAMMABLE
OPTION
PLLEN
RING
ON
OSCILLATOR
fVCO/2
PLL
fSLOW CLOCK
fCKI
CMOS
INPUT
CLOCK
PLLSEL
SYNC.
MUX
STOP
HW STOP
NOCK
SW STOP
RSTB
CLEAR NOCK
INT0
INT0EN
INT1
DEEP
SLEEP
DISABLE
SYNC.
GATE
fINTERNAL CLOCK
INTERNAL
PROCESSOR
CLOCK
Preliminary Data Sheet
February 1997
DEEP
SLEEP
SLOWCKI
INT1EN
5-4124 (F).c
Notes:
The functions in the shaded ovals are bits in the powerc control register. The functions in the nonshaded ovals are bits in the pllc control
register.
Deep sleep is the state arrived at either by a hardware or software stop of the internal processor clock.
The switching of the multiplexers and the synchronous gate is designed so that no partial clocks or glitching will occur.
When the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the ring oscillator is
powered down.
PLL select is the PLLSEL bit of pllc; PLL powerdown is the PLLEN bit of pllc.
Figure 11. Power Management Using the powerc and the pllc Registers
40
Lucent Technologies Inc.