DSP1620 Datasheet, PDF (1/114 Pages) Agere Systems – Clarification to the Serial I/O Control Register Description for the DSP1620/27/28/29 Devices

Advisory
May 1999
Clarification to the Serial I/O Control Register
Description for the DSP1620/27/28/29 Devices
Active Clock Frequency
The purpose of this advisory is to clarify the function of the serial I/O control registers in the DSP1620/27/28/29
devices. Specifically, it clarifies the function of the control register field that specifies the active clock frequency.
The device data sheets state that the active clock frequency is a ratio of the input clock frequency on the CKI
pin (DSP1627/28/29 devices) or the output clock frequency on the CKO pin (DSP1620 device). For all four
devices, the actual active clock frequency is a ratio of the internal clock frequency, which can be programmed
as either the input clock frequency on the CKI pin or the output of an internal clock synthesizer (PLL).
Table 1 summarizes information for each of the four devices. It lists the document number for each device data
sheet. For example, the data sheet for the DSP1620, entitled DSP1620 Digital Signal Processor, has the docu-
ment number DS97-321WDSP. Table 1 also lists the name of each serial I/O unit on each device, the corre-
sponding control register, the data sheet page number that describes the register, and the corresponding field
within the register that specifies the active clock frequency. For example, the DSP1620 contains two serial I/O
units named SIO and SSIO. The control register for SIO is sioc described on page 94 of the data sheet.
Bits 8—7 within sioc (CLK1 field) specify the active clock frequency of the SIO.
Table 1. Data Sheet and Serial I/O Information for the DSP1620/27/28/29 Devices
Device
Data Sheet
Document Number
DSP1620
DSP1627
DSP1628
DSP1629
DS97-321WDSP
DS96-188WDSP
DS97-040WDSP
DS96-039WDSP
Name
SIO
SSIO
SIO
SIO2
SIO
SIO2
SIO
SIO2
Control
Register
sioc
SSIOC
sioc
Serial I/O Units
Data Sheet Active Clock Frequency
Page No.
Control Field
Bits
Name
94
8—7
CLK1
96
8—7
CLK2
45
8—7
CLK
sioc
55
8—7
CLK
sioc
46
8—7
CLK
Table 2 shows a corrected description of the CLK/CLK1/CLK2 field of the serial I/O control register. The
specific correction is shown in bold type—the active clock frequency is a ratio of finternal clock, not of CKI or CKO.
Table 2. Corrected Description of CLK/CLK1/CLK2 Field
Field
CLK
CLK1
CLK2
Value
00
01
10
11
Description
Active clock frequency = finternal clock ÷ 2
Active clock frequency = finternal clock ÷ 6
Active clock frequency = finternal clock ÷ 8
Active clock frequency = finternal clock ÷ 10
DRAFT COPY