OR3TP12 Datasheet, PDF (29/128 Pages) Agere Systems – Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description (continued)
Embedded Core/FPGA Interface Signal Locations
Table 7 lists the physical locations of all signals on the embedded core/FPGA interface. Separate names are pro-
vided for dual-port and quad-port bus signals, since their functionality is port mode dependent.
Table 7. OR3TP12 FPGA/PCI Core Interface Signal Locations
Embedded Core/FPGA
Interface Site
PB1A
PB1B
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
CKTOASB5
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
FPGA Input Signal
Dual-Port Mode Quad-Port Mode
disctimerexpn
t_ready
pci_cfg_stat
treqn
datatofpga0
twdata0
datatofpga1
twdata1
datatofpga2
twdata2
datatofpga3
twdata3
datatofpga4
twdata4
datatofpga5
twdata5
datatofpga6
twdata6
datatofpga7
twdata7
datatofpga8
twdata8
datatofpga9
twdata9
datatofpga10
twdata10
datatofpga11
twdata11
datatofpga12
twdata12
datatofpga13
twdata13
datatofpga14
twdata14
datatofpga15
twdata15
(unused)
datatofpgax0
twdata16
datatofpgax1
twdata17
twlastcycn
trlastcycn
bar0
bar1
bar2
pciclk
tstatecntr0
tstatecntr1
tstatecntr2
tstatecntr3
FPGA Output Signal
Dual-Port Mode Quad-Port Mode
cfgshiftenn
twburstpendn
(unused)
(unused)
datafmfpga0
trdata0
datafmfpga1
trdata1
datafmfpga2
trdata2
datafmfpga3
trdata3
datafmfpga4
trdata4
datafmfpga5
trdata5
datafmfpga6
trdata6
datafmfpga7
trdata7
datafmfpga8
trdata8
datafmfpga9
trdata9
datafmfpga10
trdata10
datafmfpga11
trdata11
datafmfpga12
trdata12
datafmfpga13
trdata13
datafmfpga14
trdata14
datafmfpga15
trdata15
fclk2
datafmfpgax0
trdata16
datafmfpgax1
trdata17
twdataenn
trdataenn
fpga_syserror
t_abort
t_retryn
taenn
(unused)
(unused)
(unused)
(unused)
Lucent Technologies Inc.
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Lucent Technologies Inc.