OR3TP12 Datasheet, PDF (27/128 Pages) Agere Systems – Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description (continued)
Table 6. Embedded Core/FPGA Interface Signals (continued)
Symbol
I/O
Description
Clock
Domain
Target Read Data FIFO Signals (continued)
trpcihold
trburstpendn
O ^{Target Read PCI Bus Hold. For read transfers to the PCI bus, this signal}
delays the start of the data transfer (i.e., trdyn assertion). The data transfer
will begin when trpcihold is deasserted or the Target read data FIFO
becomes full. Once asserted, this signal needs to remain asserted for a min-
imum of two pciclk cycles.
O ^{Target Read Burst Control. This active-low signal directs the Target to}
insert up to eight wait-states between subsequent read data phases before
disconnect. When deasserted, the Target will disconnect immediately when
the Target read data FIFO becomes empty. If deltrn is inactive, trburst-
pendn must be driven active. Once asserted, this signal needs to remain
asserted for a minimum of two pciclk cycles.
Miscellaneous Signals
pci_intan
fclk1
fclk2
pciclk
pci_rstn
fpga_syserror
O ^{PCI Interrupt Request. This active-low signal is used to generate a PCI bus}
interrupt and is forwarded by the embedded core as intan onto the PCI bus.
Once asserted, this signal needs to remain asserted for a minimum of two
pciclk cycles.
O FPGA Clock 1 and 2. Clocks used by the Master and Target FIFO interface
O logic. fclk1 and fclk2 need to be activated for use by the Master and Target
in the FPSC configuration manager. In dual-port mode, only one of these
clocks may be active, while the other should be tied low.
I ^{PCI Clock. pciclk is a buffered version of clk for use by the FPGA applica-}
tion as the main clock, or for control signals which are in the pciclk domain
(such as t_retryn, mr_stopburstn, etc.). The FPGA may route pciclk to any
of the FPGA resources, fclk1 or fclk2, programmable clock managers, etc.
I ^{PCI Reset. This active-low signal indicates that a PCI bus reset was received}
from the PCI bus (rstn).
O ^{System Error. This pin is used by the FPGA to generate a system error on}
the PCI bus. This is passed to the PCI bus as serrn. Once asserted, this sig-
nal needs to remain asserted for a minimum of two pciclk cycles.
pciclk
pciclk
—
—
—
—
pciclk
* The source of the clock (fclk1 or fclk2) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.
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Lucent Technologies Inc.