UT8Q512E Datasheet, PDF (2/22 Pages) Aeroflex Circuit Technology – UT8Q512E 512K x 8 RadTol SRAM

A0
1
A1
2
A2
3
A3
4
A4
5
E
6
DQ0
7
DQ1
8
V_DD
9
V_SS
10
DQ2
11
DQ3
12
W
13
A5
14
A6
15
A7
16
A8
17
A9
18
36
NC
35
A18
34
A17
33
A16
32
A15
31
G
30
DQ7
29
DQ6
28
V_SS
27
V_DD
26
DQ5
25
DQ4
24
A14
23
A13
22
A12
21
A11
20
A10
19
NC
Figure 2. UT8Q512E 20ns SRAM Pinout (36)
PIN NAMES
A(18:0)
DQ(7:0)
E
W
G
V_DD
V_SS
Address
Data Input/Output
Chip Enable
Write Enable
Output Enable
Power
Ground
DEVICE OPERATION
The UT8Q512E has three control inputs called Chip Enable (E),
Write Enable (W), and Output Enable (G); 19 address inputs,
A(18:0); and eight bidirectional data lines, DQ(7:0). E controls
device selection, active, and standby modes. Asserting E enables
the device, causes I_DD to rise to its active value, and decodes the
19 address inputs to select one of 524,288 words in the memory.
W controls read and write operations. During a read cycle, G
must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
GW
X¹
X
X
0
1
1
0
1
E I/O Mode
1
3-state
0
Data in
0
3-state
0
Data out
Mode
Standby
Write
Read²
Read
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W greater than V_IH (min) and E less than V_IL
(max) defines a read cycle. Read access time is measured from
the latter of Chip Enable, Output Enable, or valid address to
valid data output.
SRAM Read Cycle 1, the Address Access in figure 4a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified t_AVQV is satisfied. Outputs
remain active throughout the entire cycle. As long as Chip
Enable and Output Enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (t_AVAV).
SRAM read Cycle 2, the Chip Enable - Controlled Access in
figure 4b, is initiated by E going active while G remains asserted,
W remains deasserted, and the addresses remain stable for the
entire cycle. After the specified t_ETQV is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable - Controlled Access in
figure 4c, is initiated by G going active while E is asserted, W
is deasserted, and the addresses are stable. Read access time is
t_GLQV unless t_AVQV or t_ETQV have not been satisfied.
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