UT8Q512E Datasheet, PDF (1/22 Pages) Aeroflex Circuit Technology – UT8Q512E 512K x 8 RadTol SRAM

Standard Products
UT8Q512E 512K x 8 RadTol SRAM
Data Sheet
November 11, 2008
FEATURES
‰ 20ns maximum (3.3 volt supply) address access time
‰ Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
‰ TTL compatible inputs and output levels, three-state
bidirectional data bus
‰ Operational environment:
- Total dose: 50 krads(Si)
- SEL Immune 110 MeV-cm²/mg
- SEU LET_TH(0.25) = 52 cm² MeV
- Saturated Cross Section 2.8E-8 cm²/bit
-<1.1E-9 errors/bit-day, Adams 90% worst case
environment geosynchronous orbit
‰ Packaging:
- 36-lead ceramic flatpack (3.831 grams)
‰ Standard Microcircuit Drawing 5962-99607
- QML Q and V compliant part
INTRODUCTION
The UT8Q512E RadTol product is a high-performance CMOS
static RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (E), an
active LOW Output Enable (G), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable (E)
and Write Enable (W) inputs LOW. Data on the eight I/O pins
(DQ₀ through DQ₇) is then written into the location specified
on the address pins (A₀ through A₁₈). Reading from the device
is accomplished by taking Chip Enable (E) and Output Enable
(G) LOW while forcing Write Enable (W) HIGH. Under these
conditions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
The eight input/output pins (DQ₀ through DQ₇) are placed in a
high impedance state when the device is deselected (E HIGH),
the outputs are disabled (G HIGH), or during a write operation
(E LOW and W LOW).
Clk. Gen.
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DQ ₀ - DQ ₇
Memory Array
1024 Rows
512x8 Columns
Data
Control
CLK
Gen.
I/O Circuit
Column Select
E
W
G
Figure 1. UT8Q512E SRAM Block Diagram
1