UT54ACS164E Datasheet, PDF (1/9 Pages) Aeroflex Circuit Technology – 8-Bit Shift Registers

UT54ACS164E/UT54ACTS164E
8-Bit Shift Registers
October, 2008
www.aeroflex.com/Logic
FEATURES
• AND-gated (enable/disable) serial inputs
• Fully buffered clock and serial inputs
• Direct clear
• 0.6μm CRH CMOS Process
- Latchup immune
• High speed
• Low power consumption
• Wide operating power supply from 3.0V to 5.5V
• Available QML Q or V processes
• 14-lead flatpack
DESCRIPTION
The UT54ACS164E and the UT54ACTS164E are 8-bit shift
registers which feature AND-gated serial inputs and an asyn-
chronous clear. The gated serial inputs (A and B) permit com-
plete control over incoming data. A low at either input inhibits
entry of new data and resets the first flip-flop to the low level
at the next clock pulse. A high-level at both serial inputs sets
the first flip-flop to the high level at the next clock pulse. Data
at the serial inputs may be changed while the clock is high or
low, providing the minimum setup time requirements are met.
Clocking occurs on the low-to-high-level transition of the clock
input.
The devices are characterized over full HiRel temperature range
of -55°C to +125°C.
PINOUT
A
B
Q_A
Q_B
Q_C
Q_D
V_SS
14-Lead Flatpack
Top View
1 14
2 13
3 12
4 11
5 10
6
9
7
8
V_DD
Q_H
Q_G
Q_F
Q_E
CLR
CLK
FUNCTION TABLE
CLR
INPUTS
CLK
A
L
X
X
H
L
X
H
↑
H
H
↑
L
H
↑
X
OUTPUTS
B
Q_A
Q_{B ...} Q_H
X
L
L
L
X
Q_A0
Q_B0
Q_H0
H
H
Q_An
Q_Gn
X
L
Q_An
Q_Gn
L
L
Q_An
Q_Gn
Notes:
1. Q_A0, Q_B0, Q_H0 = the level of Q_A, Q_B or Q_H, respectively, before the indicated
steady-state input conditions were established.
2. Q_An and Q_Gn = the level of Q_A or Q_G before the most recent ↑ transition of
the clock; indicates a one-bit shift.
LOGIC SYMBOL
(9)
CLR
(8)
CLK
A ⁽¹⁾
(2)
B
SRG8
R
C1/
&
1D
(3)
Q_A
(4)
(5) ^QB
(6) ^QC
(10) ^QD
(11) ^QE
(12) ^QF
(13) ^QG
Q_H
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
1