2N3866 Datasheet, PDF (3/5 Pages) NXP Semiconductors – Silicon planar epitaxial overlay transistors

2N3866 / 2N3866A
FUNCTIONAL
Symbol
Test Conditions
GPE
Pout
ηC
Power Gain
Output Power
Collector Efficiency
Test Circuit-Figure 1
Pin = 0.1 W, VCE = 28Vdc
f = 400 MHz, TC = 25 C
Test Circuit-Figure 1
Pin = 0.1 W, VCE = 28Vdc
f = 400 MHz, TC = 25 C
Test Circuit-Figure 1
Pin = 0.1 W, VCE = 28Vdc
f = 400 MHz, TC = 25 C
Min.
10
1.0
45
Value
Typ.
-
-
-
Max.
-
-
-
Unit
dB
Watts
%
P_IN
(R_S=50 OHMS)
8-60
L_S
P_OUT
(R_L=50 OHMS)
8-60
RFC
L₁
RFC
3-35
12
RFC
5.6 OHMS
1000
V_CE = -28V
0.9-7
Figure 1 - 400 MHz RF AMPLIFIER CIRCUIT FOR GPE, POUT, AND EFFICIENCY SPECIFICATIONS.
L1: 2 TURNS No. 18 wire, ¼” ID, 1/8” long
Ls: 2 ¾TURNS No. 18 wire, ¼” ID, 3/16” long
Capacitor values in pF unless
otherwise indicated.
.
Tuning capacitors are air variable
2N3866.PDF 10-28-02
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