AD9695 Datasheet, PDF (96/136 Pages) Analog Devices – Dual Analog-to-Digital Converter

Data Sheet
AD9695
MEMORY MAP REGISTERS
All address locations that are not included in Table 47 are not currently supported for this device and must not be written.
Table 47. Memory Map Registers
Address
Name
Bits
Analog Devices SPI Registers
0x0000
SPI
7
Configuration A
Bit Name
Soft reset mirror (self
clearing)
6 LSB first mirror
5 Address ascension
mirror
[4:3] Reserved
2 Address ascension
1 LSB first
0 Soft reset (self clearing)
0x0001
0x0002
SPI
Configuration B
Chip
configuration
(local)
[7:2] Reserved
1 Datapath soft reset
(self clearing)
0 Reserved
[7:2] Reserved
[1:0] Channel power mode
0x0003
0x0004
0x0005
Chip type
Chip ID LSB
Chip ID MSB
[7:0] Chip type
[7:0] Chip ID LSB [7:0]
[7:0] Chip ID MSB [15:8]
Settings
0
1
1
0
0
1
0
1
1
0
0
1
0
1
00
10
11
0x3
0xDE
Description
Whenever a soft reset is issued, the
user must wait 5 ms before writing to
any other register; this provides
sufficient time for the boot loader to
complete.
Do nothing.
Reset the SPI and registers (self
clearing).
Least significant bit shifted first for all
SPI operations.
Most significant bit shifted first for all
SPI operations.
Multibyte SPI operations cause
addresses to auto decrement.
Multibyte SPI operations cause
addresses to auto increment.
Reserved.
Multibyte SPI operations cause
addresses to auto decrement.
Multibyte SPI operations cause
addresses to auto increment.
Least significant bit shifted first for all
SPI operations.
Most significant bit shifted first for all
SPI operations.
Whenever a soft reset is issued, the
user must wait 5 ms before writing to
any other register; this provides
sufficient time for the boot loader to
complete.
Do nothing.
Reset the SPI and registers (self
clearing).
Reserved.
Normal operation.
Datapth soft reset (self clearing).
Reserved.
Reserved.
Channel power modes.
Normal mode (power-up).
Standby mode. Digital datapath
clocks disabled; JESD204B interface
enabled.
Power-down mode. Digital datapath
clocks disabled; digital datapath held
in reset; JESD204B interface disabled.
Chip type.
High speed ADC.
Chip ID.
AD9695.
Chip ID.
Reset Access
0x0 R/WC
0x0 R/W
0x0 R/W
0x0 R
0x0 R/W
0x0 R/W
0x0 R/WC
0x0 R
0x0 R/WC
0x0 R
0x0 R
0x0 R/W
0x3 R
R
0x0 R
Rev. 0 | Page 95 of 135