AD9695 Datasheet, PDF (102/136 Pages) Analog Devices – Dual Analog-to-Digital Converter

Data Sheet
AD9695
Address
0x011C
0x011E
0x0120
0x0121
Name
Clock Duty Cycle
Stabilizer 1
(DCS1) control
(local)
Clock Duty Cycle
Stabilizer 2
(DCS2) control
SYSREF±
Control 1
SYSREF±
Control 2
Bits Bit Name
[7:2] Reserved
1 DCS1 enable
0 DCS1 power-up
[7:2] Reserved
1 DCS2 enable
0 DCS2 power-up
7 Reserved
6 SYSREF± flag reset
5 Reserved
4 SYSREF± transition
select
Settings
0
1
0
1
0
1
0
1
0
1
0
1
3 CLK± edge select
0
1
[2:1] SYSREF± mode select 0
1
10
0 Reserved
[7:4] Reserved
[3:0] SYSREF± N-shot ignore 0000
counter select
0001
0010
0011
1110
1111
Description
Reserved
Clock DCS1 enable.
DCS1 bypassed.
DCS1 enabled.
Clock DCS1 power-up.
DCS1 powered down.
DCS1 powered up.
Reserved.
Clock DCS2 enable.
DCS2 bypassed.
DCS2 enabled.
Clock DCS2 power-up.
DCS2 powered down.
DCS2 powered up.
Reserved.
Normal flag operation.
SYSREF flags held in reset (setup/hold
error flags cleared).
Reserved.
SYSREF is valid on low to high trans-
itions using the selected CLK± edge.
When changing this setting, SYSREF±
mode select must be set to disabled.
SYSREF is valid on high to low
transitions using the selected CLK±
edge. When changing this setting,
SYSREF± mode select must be set to
disabled.
Captured on rising edge of CLK± input.
Captured on falling edge of CLK± input.
Disabled.
Continuous.
N-shot.
Reserved.
Reserved.
Next SYSREF only (do not ignore).
Ignore the first SYSREF± transition.
Ignore the first two SYSREF± transitions.
Ignore the first three SYSREF±
transitions.
…
Ignore the first 14 SYSREF± transitions.
Ignore the first 15 SYSREF± transitions.
Reset
0x0
0x1
0x1
0x0
0x1
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R
R
R/W
Rev. 0 | Page 101 of 135