AD9633 Datasheet, PDF (9/40 Pages) Analog Devices – Quad, 12-Bit, 80 MSPS/105 MSPS

Data Sheet
VIN±x
CLK–
CLK+
DDR
SDR
DCO–
DCO+
DCO–
DCO+
FCO–
BITWISE
MODE
FCO+
D0–A
D0+A
D1–A
D1+A
FCO–
BYTEWISE
MODE
FCO+
D0–A
D0+A
D1–A
D1+A
N–1
t_A
t_EH
t_CPD
N
t_EL
AD9633
N+1
t_FCO
t_FRAME
t_PD
t_DATA
D08 D06 D04 D02 LSB D08 D06 D04 D02 LSB D08 D06 D04 D02
N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15
MSB
N – 17
D07
N – 17
D05
N – 17
D03
N – 17
D01
N – 17
MSB
N – 16
D07
N – 16
t_LD
D05 D03
N – 16 N – 16
D01
N – 16
MSB
N – 15
D07
N – 15
D05
N – 15
D03
N – 15
D04 D03 D02 D01 LSB D04 D03 D02 D01 LSB D04 D03 D02 D01
N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15
MSB D08 D07 D06 D05 MSB D08 D07 D06 D05 MSB D08 D07 D06
N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15
Figure 5. 10-Bit DDR/SDR, Two-Lane, 2× Frame Mode
VIN±x
CLK–
CLK+
DCO–
DCO+
FCO–
FCO+
D0–x
D0+x
N–1
t_A
t_EH
t_CPD
N
t_EL
t_FCO
t_FRAME
t_PD
t_DATA
MSB D10 D9
D8
D7
D6
D5
D4
D3 D2
D1
D0 MSB D10
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16
Figure 6. Wordwise DDR, One-Lane, 1× Frame, 12-Bit Output Mode
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