AD9633 Datasheet, PDF (1/40 Pages) Analog Devices – Quad, 12-Bit, 80 MSPS/105 MSPS

Data Sheet
Quad, 12-Bit, 80 MSPS/105 MSPS/
125 MSPS, Serial LVDS 1.8 V ADC
AD9633
FEATURES
1.8 V supply operation
Low power: 100 mW per channel at 125 MSPS with scalable
power options
SNR = 71 dB (to Nyquist)
SFDR = 91 dBc (to Nyquist)
DNL = ±0.3 LSB (typical); INL = ±0.5 LSB (typical)
Serial LVDS (ANSI-644, default) and low power, reduced
signal option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Programmable output clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical ultrasound
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment
GENERAL DESCRIPTION
The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS
analog-to-digital converter (ADC) with an on-chip sample-and-
hold circuit designed for low cost, low power, small size, and
ease of use. The product operates at a conversion rate of up to
125 MSPS and is optimized for outstanding dynamic performance
and low power in applications where a small package size is
critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled.
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
VIN+A
VIN–A
VIN+B
VIN–B
RBIAS
VREF
SENSE
AGND
VIN+C
VIN–C
VIN+D
VIN–D
12
PIPELINE
ADC
DIGITAL
SERIALIZER
12
PIPELINE
ADC
DIGITAL
SERIALIZER
REF
SELECT
1V _AD9633
12
PIPELINE
ADC
DIGITAL
SERIALIZER
12
PIPELINE
ADC
DIGITAL
SERIALIZER
VCM
SERIAL PORT
INTERFACE
CLOCK
MANAGEMENT
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
D0+A
D0–A
D1+A
D1–A
D0+B
D0–B
D1+B
D1–B
FCO+
FCO–
D0+C
D0–C
D1+C
D1–C
D0+D
D0–D
D1+D
D1–D
DCO+
DCO–
Figure 1.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
output clock and data alignment and digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9633 is available in a RoHS-compliant, 48-lead LFCSP.
It is specified over the industrial temperature range of −40°C to
+85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint. Four ADCs are contained in a small, space-
saving package.
2. Low power of 100 mW/channel at 125 MSPS with scalable
power options.
3. Pin compatible to the AD9253 14-bit quad ADC.
4. Ease of Use. A data clock output (DCO) operates at
frequencies of up to 375 MHz and supports double data
rate (DDR) operation.
5. User Flexibility. The SPI control offers a wide range of flexible
features to meet specific system requirements.
Rev. 0
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