AD9501_15 Datasheet, PDF (9/12 Pages) Analog Devices – Digitally Programmable Delay Generator

AD9501
Programmable Pulse Generator
In Figure 9, two AD9501 units are triggered from a common
clock signal. Their outputs go to the inputs of an RS flip-flop.
A digital delay value is applied as an input to each with
AD9501 #2 typically having a larger value than AD9501 #1.
with t_TOT being equal to each AD9501’s minimum propagation
delay (t_PD) plus programmed delay (t_D). If both AD9501s are
set for the same full-scale delay range, their minimum propagation
delays will be approximately the same, and the pulse width will
be approximately equal to the difference in programmed delays.
Digital Delay Detector
CLOCK IN
TRIGGER ^{AD9501 #1}
An unknown digital delay can be measured by applying a repeti-
DIGITAL
DATA
OUTPUT ^Q1
tive clock to the circuit shown in Figure 10.
DECODER
LATCH
RESET
S Q ^Q0
OUTPUT
The pictured delay detector works in a manner similar to a
successive-approximation ADC; in this circuit, however, a D-type
flip-flop replaces the ADC’s voltage comparator.
LATCH AD9501 #2
R
OBSOLETE ^{␮P BUS}
DIGITAL
DATA
OUTPUT ^Q2
TRIGGER _RESET
8
CLOCK IN
t_D #1
Q₁
t_D #2
Q₂
t_D #1
t_D #2
Q₀
Figure 9. Programmable Pulse Delay Generator
To calibrate the circuit, short out the unknown delay and apply
the clock input to both AD9501 units.
AD9501 #1 should be programmed so its delay is greater than
the zero-set programmed delay of AD9501 #2. To accomplish
this, continue to apply clock pulses and increment the digital
data into AD9501 #1 until the output of the successive-approxi-
mation register (SAR) is 02H (00000010) or greater. At this
point, the delay through AD9501 #1 is slightly longer than the
delay through AD9501 #2, making it possible to use the SAR
output as the zero reference point for measuring the unknown
delay when it is reinserted into the circuit.
This calibration procedure compensates for the setup time of
the flip-flop, stray circuit delays, and other nonideal characteristics
that are an inherent part of any circuit.
Eight cycles of the clock input are required to determine the
value of the unknown delay.
As shown by the timing portion of the diagram, changing the
delay value from one clock cycle to the next generates a pseudo-
random pulse whose leading and trailing edge delays are controlled
relative to Clock In. The dashed lines illustrate how the
programmed delays of the AD9501 components control both
the timing and width of the generator output.
The frequency (f) and pulse width (t_pw) of the pulse generator
can be determined as follows:
and:
f = f_{CLOCK IN}
CLOCK IN
GROUND
00_H
8
AD9501 #1
TRIGGER
LATCH
OUTPUT ^Q1
DIGITAL
DATA
RESET
AD9501 #2
TRIGGER
LATCH OUTPUT
DIGITAL
DATA
RESET
UNKNOWN
DELAY
D
Q
CLK
t _pw = t_{TOT 2} – t_{TOT 1}
RESET
8-BIT SUCCESSIVE
APPROX. REGISTER
Figure 10. Digital Delay Detector
REV. B
–9–