AD9501_15 Datasheet, PDF (6/12 Pages) Analog Devices – Digitally Programmable Delay Generator

AD9501
Offset between the two levels is necessary for three reasons.
First, offset allows the ramp to reset and settle without re-entering
the voltage range of the DAC. Second, the DAC may overshoot
as it switches to its most positive value (00_H); this can lead to
false output pulses if there is no offset between the ramp reset
voltage and the upper reference. Overshoot on the ramp can also
lead to false outputs without the offset. Finally, the ramp is
slightly nonlinear for a short interval when it is first started;
the offset shifts the most positive DAC level below this
Caution is urged when using resistance in series with Pin 8. The
possibility of false output pulses, as discussed above, is increased
under these circumstances. Using resistance in series with Pin 8
is recommended only when matching minimum delays between
two or more AD9501 devices; it is not recommended if using a
single AD9501. Changing the resistance between Pin 8 and
ground from 0 kW to 10 kW varies the ramp generator delay by
approximately 35%.
10␮s
nonlinear region and maintains ramp linearity for short
programmed delay settings.
500pF
Pin 8 of the AD9501 is called OFFSET ADJUST (see Func-
1␮s
OBSOLETE tional Block Diagram) and allows the user to control the amount of
offset separating the initial ramp voltage and the most positive
DAC reference. This, in turn, causes the ramp generator delay to
vary.
Figure 3 shows differences in timing that occur if OFFSET
ADJUST Pin 8 is grounded or open. The variable ramp generator
delay is the major component of the three components that
comprise minimum delay (t_PD) and, therefore, is affected by the
connection to Pin 8.
It is preferable to ground Pin 8 because the smaller offset that
results from leaving it open increases the possibility of false
output pulses. When grounding the pin, it should be grounded
directly or connected to the ground through a resistor or potentio-
meter with a value of 10 kW or less.
80
100ns
100pF
50pF
10pF
0pF
10ns
10
100
1k
10k
R_SET – ⍀
Figure 4. RC Values vs. Full-Scale Delay Range (t_DFS)
The full-scale delay range (t_DFS) can be calculated from the
equation:
t_DFS = R_SET ¥ (C_EXT + 8.5 pF) ¥ 3.84
Whenever full-scale delay range is 326 ns or less, C_EXT should
be left open. Additional capacitance and/or larger values of R_SET
70
increase the linear ramp settling time, which reduces the maxi-
C_EXT = 0pF
mum trigger rate. When delays longer than 326 ns are required,
60
up to 500 pF can be connected from C_EXT to +V_S. To preserve
OFFSET ADJUST
50 _{(PIN 8) GROUNDED}
the unit’s low drift performance, both R_SET and C_EXT should
have low temperature coefficients. Resistors that are used should
40
be 1% metal film types.
30
20
OFFSET ADJUST
(PIN 8) OPEN
10
0
0 40 80 120 160 200 240 280 320 360 400
FULL-SCALE DELAY RANGE – ns
The programmed delay (t_D) is set by the DAC inputs, D₀–D₇.
The minimum delay through the AD9501 corresponds to an
input code of 00_H, and FF_H gives the full-scale delay. Any
programmed delay can be approximated by
t_D = (DAC code / 256) ¥ t_DFS
Figure 3. Minimum Delay (t_PD) vs. Full-Scale Delay Range (t_DFS)
Total delay through the AD9501 for any given DAC code is
equal to
t_TOTAL = t_D + t_PD
–6–
REV. B