AD9411 Datasheet, PDF (9/28 Pages) Analog Devices – 10-Bit, 170/200 MSPS 3.3 V A/D Converter

Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
S5
2, 42–46,49–52
3, 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31,
32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100
5, 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34,
39, 40, 88, 89, 90, 94, 95, 98, 99
6
7
DNC
AGND
AVDD
S1
LVDSBIAS
10
11
21
22
36
37
47, 54, 62, 75, 83
48, 53, 61, 67, 74, 82
SENSE
VREF
VIN+
VIN–
CLK+
CLK–
DRVDD
DRGND
56
D0+
57
D1–
58
D1+
59
D2–
60
D2+
63
DCO–
64
DCO+
65
D3–
66
D3+
68
D4–
69
D4+
70
D5–
71
D5+
72
D6–
73
D6+
76
D7–
77
D7+
78
D8–
79
D8+
80
D9–
81
D9+
84
OR–
85
OR+
AD9411
Function
Full-Scale Adjust Pin. AVDD sets FS = 0.768 V p-p differential;
GND sets FS = 1.536 V p-p differential.
Do Not Connect.
Analog Ground. AGND and DRGND should be tied together to a common
ground plane.
3.3 V Analog Supply.
Data Format Select. GND = binary; AVDD = twos complement.
Set Pin for LVDS Output Current. Place a 3.74 kΩ resistor terminated to
ground.
Reference Mode Select Pin. Float for internal reference operation.
1.235 V Reference Input/Output. Function depends on SENSE.
Analog Input. True.
Analog Input. Complement.
Clock Input. True (LVPECL levels).
Clock Input. Complement (LVPECL levels).
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Digital Output Ground. AGND and DRGND should be tied together to a
common ground plane.
D0 True Output Bit.
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
Data Clock Output. Complement.
Data Clock Output. True.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
Overrange Complement Output Bit.
Overrange True Output Bit.
Rev. A | Page 9 of 28