AD9411 Datasheet, PDF (1/28 Pages) Analog Devices – 10-Bit, 170/200 MSPS 3.3 V A/D Converter

FEATURES
SNR = 60 dB @ fIN up to 70 MHz @ 200 MSPS
ENOB of 9.8 @ fIN up to 70 MHz @ 200 MSPS (–0.5 dBFS)
SFDR = 80 dBc @ fIN up to 70 MHz @ 200 MSPS (–0.5 dBFS)
Excellent linearity:
DNL = ±0.15 LSB (typical)
INL = ±0.25 LSB (typical)
LVDS output levels
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.25 W typical @ 200 MSPS
1.5 V input voltage range
3.3 V supply operation
Output data format option
Clock duty cycle stabilizer
Pin compatible to LVDS mode AD9430
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
GENERAL DESCRIPTION
The AD9411 is a 10-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates up to a 200 MSPS conversion rate
and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary
functions, including track-and-hold (T/H) and reference, are
included on the chip to provide a complete conversion solution.
The ADC requires a 3.3 V power supply and a differential
sample clock for full performance operation. The digital outputs
are LVDS compatible and support both twos complement and
offset binary format. A data clock output is available to ease
data capture.
Fabricated on an advanced BiCMOS process, the AD9411 is
available in a 100-lead surface-mount plastic package (e-PAD
TQFP-100) specified over the industrial temperature range
(–40°C to +85°C).
Rev. A
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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10-Bit, 170/200 MSPS
3.3 V A/D Converter
AD9411
FUNCTIONAL BLOCK DIAGRAM
SENSE VREF AGND DRGND DRVDD AVDD
SCALABLE
REFERENCE
AD9411
VIN+
VIN–
TRACK
AND
HOLD
ADC
10-BIT
PIPELINE
10
/
CORE
LVDS
OUTPUTS
DATA,
OVERRANGE
IN LVDS
CLK+
CLK–
CLOCK
MANAGEMENT
LVDS TIMING
S1
S5
Figure 1.
DCO+
DCO–
PRODUCT HIGHLIGHTS
1. High performance.
Maintains 60 dB SNR @ 200 MSPS with a 70 MHz input.
2. Low power.
Consumes only 1.25 W @ 200 MSPS.
3. Ease of use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold function provide flexibility in system
design. Use of a single 3.3 V supply simplifies system
power supply design.
4. Out-of-range (OR).
The OR output bit indicates when the input signal is
beyond the selected input range.
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