AD71028_15 Datasheet, PDF (9/20 Pages) Analog Devices – Dual Digital BTSC Encoder with Integrated DAC

CLK27_PA, CLK27_PB
Input pins to the divide-by-1125 block. If an external PLL is
used to generate the audio master clock, the 27 MHz video
master clock may be applied to these pins where it is divided by
1125 to produce a 24 kHz feedback clock to the external PLL
phase detector.
DIV1_PA, DIV1_PB
Output of divide-by-1024 circuit. Divides the master clock
signal by 1024 (or 512 when DOUBLE is asserted). Used to
interface to external PLL.
DIV2_PA, DIV2_PB
Output of divide-by-1125 circuit. Divides the master-clock
signal by 1125. Used to interface to external PLL. The output
signal is a pulse with a duration of one master clock, and should
therefore be used with edge-triggered phase detectors.
REFCAP
Analog reference voltage input. The nominal REFCAP input
voltage is 2.5 V; the analog gain scales directly with the voltage
on this pin. Any ac signal on this pin will cause distortion, and
therefore a large decoupling capacitor should be used to ensure
that the voltage on REFCAP is clean. The input impedance of
REFCAP is greater than 1 MΩ.
FILTCAP
Filter cap point. This pin is used to reduce the noise on an
internal biasing point in order to provide the highest
performance. It may not be necessary to connect this pin,
depending on the quality of the layout and grounding used in
the application circuit.
AD71028
DVDD
Digital VDD for core. 5 V nominal.
ODVDD
Digital VDD for all digital outputs. Variable from 2.7 V to 5.5 V.
DGND
Digital ground.
AVDD
Analog VDD. 5 V nominal. Bypass capacitors should be placed
close to the pins and connected directly to the analog ground
plane.
AGND
Analog ground.
OUTA+, OUTA–
Differential analog outputs for Processor A. The nominal output
voltage for a 1 kHz 0 dB mono input signal is 600 mV rms. This
level may be adjusted by writing to SPI location 258.
OUTB+, OUTB–
Differential analog outputs for Processor B. The nominal output
voltage for a 1 kHz 0 dB mono input signal is 600 mV rms. This
level may be adjusted by writing to SPI location 770.
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