AD5665R_15 Datasheet, PDF (9/36 Pages) Analog Devices – Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference, IC Interface

Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Parameter Test Conditions²
Min
t12
Standard mode
Fast mode
High speed mode, CB = 100 pF
10
High speed mode, CB = 400 pF
20
t13
Standard mode
10
Fast mode
10
High speed mode
10
t14
Standard mode
300
Fast mode
300
High speed mode
30
t15
Standard mode
20
Fast mode
20
High speed mode
20
tSP4
Fast mode
0
High speed mode
0
Max
Unit
Description
300
ns
tFCL, fall time of SCL signal
300
ns
40
ns
80
ns
ns
LDAC pulse width low
ns
ns
ns
Falling edge of ninth SCL clock pulse of last byte
of a valid write to LDAC falling edge
ns
ns
ns
CLR pulse width low
ns
ns
50
ns
Pulse width of spike suppressed
10
ns
1 _{See Figure 3. High speed mode timing specification applies only to the AD5625RBRUZ-2/AD5625RBRUZ-2REEL7 and AD5665RBRUZ-2/AD5665RBRUZ-2REEL7.}
2 _{CB refers to the capacitance on the bus line.}
3 _{The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC}
behavior of the part.
4 _{Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.}
SCL
SDA
t₇
PS
t₁₁
t₂
t₆
t₄
t₁₂
t₁
t₃
t₆
t₅
t₁₀
S
LDAC*
CLR
t₁₅
*ASYNCHRONOUS LDAC UPDATE MODE.
Figure 3. 2-Wire Serial Interface Timing Diagram
t₈
t₉
t₁₄
P
t₁₃
Rev. C | Page 9 of 36