AD5665R_15 Datasheet, PDF (30/36 Pages) Analog Devices – Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference, IC Interface

AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
POWER-DOWN MODES
Command 100 is reserved for the power-up/power-down
function. The power-up/power-down modes are programmed
by setting Bit DB5 and Bit DB4. This defines the output state of
the DAC amplifier, as shown in Table 15. Bit DB3 to Bit DB0
determine to which DAC or DACs the power-up/power-down
command is applied. Setting one of these bits to 1 applies the
power-up/power-down state defined by DB5 and DB4 to the
corresponding DAC. If a bit is 0, the state of the DAC is
unchanged. Figure 70 shows the contents of the input shift
register for the power-up/power-down command.
When Bit DB5 and Bit DB4 are set to 0, the part works normally
with its normal power consumption of 1 mA at 5 V. However,
for the three power-down modes, the supply current falls to
480 nA at 5 V. Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This allows the
output impedance of the part to be known while the part is in
power-down mode. The outputs can either be connected
internally to GND through a 1 kΩ or 100 kΩ resistor or be left
open-circuited (three-state) as shown in Figure 67.
Note that the 14-lead TSSOP models offer the power-down
function when the part is operated with a VDD of 3.6 V to 5.5 V.
The 10-lead LFCSP models offer the power-down function
when the part is powered with a VDD of 2.7 V to 5.5 V.
Table 15. Modes of Operation for the AD56x5R/AD56x5
DB5
DB4
Operating Mode
0
0
Normal operation
Power-down modes
0
1
1 kΩ pull-down resistor to GND
1
0
100 kΩ pull-down resistor to GND
1
1
Three-state, high impedance
RESISTOR
STRING DAC
AMPLIFIER
V_OUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 69. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit power-
down is typically 4 μs for VDD = 5 V or VDD = 3 V.
R
S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
X
1
0
0 A2 A1 A0 X
X
X
X
X
X
X
X
X
X PD1 PD0 DAC D DAC C DAC B DAC A
COMMAND
DAC ADDRESS
(DON’T CARE)
DON’T CARE
DON’T CARE
POWER-
DOWN MODE
DAC SELECT
(1 = DAC SELECTED)
Figure 70. Power-Up/Power-Down Command
Rev. C | Page 30 of 36