ADAU1372_15 Datasheet, PDF (84/92 Pages) Analog Devices – Quad ADC, Dual DAC, Low Latency, Low Power Codec

ADAU1372
Bits Bit Name
0
INT_0_EN
Settings
0
1
Description
ASRC Interpolator 0 enable.
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ANALOG BIAS CONTROL 0 REGISTER
Address: 0x46, Reset: 0x00, Name: BIAS_CONTROL0
Data Sheet
Reset
0x0
Access
R/W
Table 77. Bit Descriptions for BIAS_CONTROL0
Bits Bit Name
Settings Description
[7:6] HP_IBIAS
Headphone output bias current setting. Higher bias currents result in higher
performance.
00 Normal operation (default)
01 Extreme power saving.
10 Enhanced performance.
11 Power saving.
[5:4] AFE_IBIAS01
Analog Front-End 0 and Analog Front-End 1 bias current setting. Higher bias
currents result in higher performance.
00 Normal operation (default)
01 Extreme power saving.
10 Enhanced performance.
11 Power saving.
[3:2] ADC_IBIAS23
ADC2 and ADC3 bias current setting. Higher bias currents result in higher
performance.
00 Normal operation (default)
01 Reserved.
10 Enhanced performance.
11 Power saving.
[1:0] ADC_IBIAS01
ADC0 and ADC1 bias current setting. Higher bias currents result in higher
performance.
00 Normal operation (default)
01 Reserved.
10 Enhanced performance.
11 Power saving.
Reset Access
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
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