ADUC841BSZ62-3 Datasheet, PDF (82/88 Pages) Analog Devices – MicroConverter® 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU

ADuC841/ADuC842/ADuC843
Parameter
SPI MASTER MODE TIMING (CPHA = 1)
Min
Typ
tSL
SCLOCK Low Pulse Width¹
476
tSH
SCLOCK High Pulse Width¹
476
tDAV
Data Output Valid after SCLOCK Edge
tDSU
Data Input Setup Time before SCLOCK Edge
100
tDHD
Data Input Hold Time after SCLOCK Edge
100
tDF
Data Output Fall Time
10
tDR
Data Output Rise Time
10
tSR
SCLOCK Rise Time
10
tSF
SCLOCK Fall Time
10
1 _{Characterized under the following conditions:}
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.
b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
Max
50
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLOCK
(CPOL = 0)
SCLOCK
(CPOL = 1)
MOSI
MISO
t_SH
t_SL
t_SR
t_DAV
t_DF
MSB
t_DR
BITS 6–1
MSB IN
BITS 6–1
t_DSU
t_DHD
Figure 91. SPI Master Mode Timing (CPHA = 1)
t_SF
LSB
LSB IN
Rev. 0 | Page 82 of 88