ADE7116_15 Datasheet, PDF (82/152 Pages) Analog Devices – Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
8052 MCU CORE ARCHITECTURE
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 have an 8052 MCU core and use the 8052 instruction
set. Some of the standard 8052 peripherals, such as the UART,
have been enhanced. This section describes the standard 8052
core and enhancements that have been made to it in the
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569.
The special function register (SFR) space is mapped into the upper
128 bytes of internal data memory space and is accessed by direct
addressing only. It provides an interface between the CPU and
all on-chip peripherals. See Figure 81 for a block diagram of the
programming model for the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569 via the SFR area.
All registers except the program counter (PC), instruction
register (IR), and the four general-purpose register banks
reside in the SFR area. The SFR registers include control,
configuration, and data registers that provide an interface
between the CPU and all on-chip peripherals.
256 BYTES
GENERAL-
PURPOSE
RAM
STACK
REGISTER
BANKS
16kB ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE
PROGRAM/DATA
MEMORY
8052
COMPATIBLE
CORE
PC
IR
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
256 BYTES XRAM
ENERGY
MEASUREMENT
POWER
MANAGEMENT
RTC
LCD DRIVER
TEMPERATURE
ADC
BATTERY
ADC
OTHER ON-CHIP
PERIPHERALS:
• SERIAL I/O
• WDT
• TIMERS
Figure 81. Block Diagram Showing Programming Model via the SFRs
MCU REGISTERS
The registers used by the MCU are summarized in this section.
Table 56. 8052 SFRs
SFR
ACC
B
PSW
PCON
DPL
DPH
DPTR
SP
CFG
Address
0xE0
0xF0
0xD0
0x87
0x82
0x83
0x82 and 0x83
0x81
0xAF
Bit Addressable
Yes
Yes
Yes
No
No
No
No
No
No
Description
Accumulator.
Auxiliary math.
Program status word (see Table 57).
Program control (see Table 58).
Data pointer low (see Table 59).
Data pointer high (see Table 60).
Data pointer (see Table 61).
Stack pointer (see Table 62).
Configuration (see Table 63).
Table 57. Program Status Word SFR (PSW, Address 0xD0)
Bit
Bit Address Mnemonic
Description
7
0xD7
CY
Carry flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
6
0xD6
AC
Auxiliary carry flag. Modified by ADD and ADDC instructions.
5
0xD5
F0
General-purpose flag available to the user.
[4:3] 0xD4, 0xD3
RS1, RS0
Register bank select bits.
RS1
RS0
Selected Bank
0
0
0
0
1
1
1
0
2
1
1
3
2
0xD2
OV
Overflow flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
1
0xD1
F1
General-purpose flag available to the user.
0
0xD0
P
Parity bit. The number of bits set in the accumulator added to the value of the parity bit is
always an even number.
Rev. B | Page 82 of 152