ADV7180_12 Datasheet, PDF (80/120 Pages) Analog Devices – 10-Bit, 4× Oversampling SDTV Video Decoder

ADV7180
Data Sheet
Address
Dec Hex Register Name
155 9B Letterbox 1
156 9C Letterbox 2
157 9D Letterbox 3
178 B2 CRC enable
195 C3 ADC Switch 1
196 C4 ADC Switch 2
220 DC Letterbox Control 1
221 DD Letterbox Control 2
222 DE ST Noise Readback 1
223 DF ST Noise Readback 2
224 E0 Reserved
225 E1 SD Offset Cb
226 E2 SD Offset Cr
227 E3 SD Saturation Cb
228 E4 SD Saturation Cr
229 E5 NTSC V bit begin
230 E6 NTSC V bit end
231 E7 NTSC F bit toggle
232 E8 PAL V bit begin
233 E9 PAL V bit end
234 EA PAL F bit toggle
235 EB Vblank Control 1
236 EC Vblank Control 2
243 F3 AFE_CONTROL 1
244 F4
248 F8
249 F9
Drive strength
IF comp control
VS mode control
251 FB Peaking control
252 FC Coring threshold
RW 7
6
R LB_LCT[7]
LB_LCT[6]
R LB_LCM[7]
LB_LCM[6]
R LB_LCB[7]
LB_LCB[6]
W
RW Reserved
MUX1[2]
RW MAN_MUX_EN
RW
RW LB_SL[3]
LB_SL[2]
R
R ST_NOISE[7] ST_NOISE[6]
5
LB_LCT[5]
LB_LCM[5]
LB_LCB[5]
4
LB_LCT[4]
LB_LCM[4]
LB_LCB[4]
3
LB_LCT[3]
LB_LCM[3]
LB_LCB[3]
MUX1[1]
MUX1[0]
LB_SL[1]
LB_TH[4]
LB_SL[0]
ST_NOISE[5] ST_NOISE[4]
Reserved
Reserved
LB_TH[3]
LB_EL[3]
ST_NOISE_VLD
ST_NOISE[3]
RW SD_OFF_Cb[7]
RW SD_OFF_Cr[7]
RW SD_SAT_Cb[7]
RW SD_SAT_Cr[7]
RW NVBEGDELO
RW NVENDDELO
RW NFTOGDELO
RW PVBEGDELO
RW PVENDDELO
RW PFTOGDELO
RW NVBIOLCM[1]
RW NVBIOCCM[1]
RW
SD_OFF_Cb[6]
SD_OFF_Cr[6]
SD_SAT_Cb[6]
SD_SAT_Cr[6]
NVBEGDELE
NVENDDELE
NFTOGDELE
PVBEGDELE
PVENDDELE
PFTOGDELE
NVBIOLCM[0]
NVBIOCCM[0]
RW
RW
RW
RW PEAKING_
GAIN[7]
RW DNR_TH2[7]
PEAKING_
GAIN[6]
DNR_TH2[6]
SD_OFF_Cb[5] SD_OFF_Cb[4]
SD_OFF_Cr[5] SD_OFF_Cr[4]
SD_SAT_Cb[5] SD_SAT_Cb[4]
SD_SAT_Cr[5] SD_SAT_Cr[4]
NVBEGSIGN NVBEG[4]
NVENDSIGN NVEND[4]
NFTOGSIGN NFTOG[4]
PVBEGSIGN PVBEG[4]
PVENDSIGN PVEND[4]
PFTOGSIGN PFTOG[4]
NVBIELCM[1] NVBIELCM[0]
NVBIECCM[1] NVBIECCM[0]
DR_STR[1] DR_STR[0]
SD_OFF_Cb[3]
SD_OFF_Cr[3]
SD_SAT_Cb[3]
SD_SAT_Cr[3]
NVBEG[3]
NVEND[3]
NFTOG[3]
PVBEG[3]
PVEND[3]
PFTOG[3]
PVBIOLCM[1]
PVBIOCCM[1]
AA_FILT_
MAN_OVR
DR_STR_C[1]
PEAKING_
GAIN[5]
DNR_TH2[5]
PEAKING_
GAIN[4]
DNR_TH2[4]
VS_COAST_
MODE[1]
PEAKING_
GAIN[3]
DNR_TH2[3]
2
LB_LCT[2]
LB_LCM[2]
LB_LCB[2]
CRC_ENABLE
MUX0[2]
MUX2[2]
LB_TH[2]
LB_EL[2]
ST_NOISE[10]
ST_NOISE[2]
SD_OFF_Cb[2]
SD_OFF_Cr[2]
SD_SAT_Cb[2]
SD_SAT_Cr[2]
NVBEG[2]
NVEND[2]
NFTOG[2]
PVBEG[2]
PVEND[2]
PFTOG[2]
PVBIOLCM[0]
PVBIOCCM[0]
AA_FILT_EN[2]
DR_STR_C[0]
IFFILTSEL[2]
VS_COAST_
MODE[0]
PEAKING_
GAIN[2]
DNR_TH2[2]
1 _{This feature applies to the 48-lead, 40-lead, and 32-lead LFCSP only because VS or FIELD is shared on a single pin.}
2 _{This feature applies to the 64-lead and 48-lead LQFP only.}
1
LB_LCT[1]
LB_LCM[1]
LB_LCB[1]
MUX0[1]
MUX2[1]
LB_TH[1]
LB_EL[1]
ST_NOISE[9]
ST_NOISE[1]
0
LB_LCT[0]
LB_LCM[0]
LB_LCB[0]
MUX0[0]
MUX2[0]
LB_TH[0]
LB_EL[0]
ST_NOISE[8]
ST_NOISE[0]
Reset
Value
(Hex)
00011100 1C
xxxxxxxx 00
0xxxxxxx 00
10101100 AC
01001100 4C
SD_OFF_Cb[1]
SD_OFF_Cr[1]
SD_SAT_Cb[1]
SD_SAT_Cr[1]
NVBEG[1]
NVEND[1]
NFTOG[1]
PVBEG[1]
PVEND[1]
PFTOG[1]
PVBIELCM[1]
PVBIECCM[1]
AA_FILT_EN[1]
DR_STR_S[1]
IFFILTSEL[1]
EXTEND_VS_
MIN_FREQ
PEAKING_
GAIN[1]
DNR_TH2[1]
SD_OFF_Cb[0]
SD_OFF_Cr[0]
SD_SAT_Cb[0]
SD_SAT_Cr[0]
NVBEG[0]
NVEND[0]
NFTOG[0]
PVBEG[0]
PVEND[0]
PFTOG[0]
PVBIELCM[0]
PVBIECCM[0]
AA_FILT_EN[0]
DR_STR_S[0]
IFFILTSEL[0]
EXTEND_VS_
MAX_FREQ
PEAKING_
GAIN[0]
DNR_TH2[0]
10000000 80
10000000 80
10000000 80
10000000 80
00100101 25
00000100 04
01100011 63
01100101 65
00010100 14
01100011 63
01010101 55
01010101 55
00000000 00
xx010101 15
00000000 00
00000011 03
01000000 40
00000100 04
Rev. E | Page 80 of 120