AD9161 Datasheet, PDF(80/139 Page)

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AD9161 Datasheet, PDF (80/139 Pages) –

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AD9161/AD9162

Data Sheet

START-UP SEQUENCE

A number of steps is required to program the AD9161/AD9162

to the proper operating state after the device is powered up. This

sequence is divided into several steps, and is listed in Table 43,

Table 44, and Table 45, along with an explanation of the purpose of

each step. Private registers are reserved but must be written for

proper operation. Blank cells in Table 43 to Table 45 mean that

the value depends on the result as described in the description

column.

The AD9161/AD9162 are calibrated at the factory as part of the

automatic test program. The configure DAC start-up sequence

loads the factory calibration coefficients, as well as configures

some parameters that optimize the performance of the DAC

and the DAC clock DLL (see Table 43). Run this sequence

whenever the DAC is powered down or reset.

The configure JESD204B sequence configures the SERDES

block and then brings up the links (see Table 44). First, run the

configure DAC start-up sequence, then run the configure

JESD204B sequence.

Follow the configure NCO sequence if using the NCO (see

Table 45). Note that the NCO can be used in NCO only mode

or in conjunction with synthesized data from the SERDES data

interface. Only one mode can be used at a time and this mode is

selected in the second step in Table 45. The configure DAC

start-up sequence is run first, then the configure NCO sequence.

Table 43. Configure DAC Start-Up Sequence After Power-Up

R/W Register

Value Description

W 0x000

0x18 Configure the device for 4-wire serial port operation (optional: leave at the default of 3-wire SPI)

W 0x0D2

0x52 Reset internal calibration registers (private)

W 0x0D2

0xD2 Clear the reset bit for the internal calibration registers (private)

W 0x606

0x02 Configure the nonvolatile random access memory (NVRAM) (private)

W 0x607

0x00 Configure the NVRAM (private)

W 0x604

0x01 Load the NVRAM. Loads factory calibration factors from the NVRAM. (private)

R 0x003, 0x004, 0x005, N/A1 (Optional) read CHIP_TYPE, PROD_ID[15:0], PROD_GRADE, and DEV_REVISION from Register 0x003,

0x006

R 0x604, Bit 1

0b1 (Optional) read the boot loader pass bit in Register 0x604, Bit 1 = 0b1 to indicate a successful boot

load

W 0x058

0x03 Enable the band gap reference (private)

W 0x090

0x1E Power up the DAC clock DLL

W 0x080

0x00 Enable the clock receiver

W 0x040

0x00 Enable the DAC bias circuits

W 0x020

0x0F Optional. Enable the interrupts

W 0x09E

0x85 Configure DAC analog parameters (private)

W 0x091

0xE9 Enable the DAC clock DLL

R 0x092, Bit 0

0b1 Check DLL_STATUS; set Register 0x092, Bit 0 = 1 to indicate the DAC clock DLL is locked to the DAC

clock input

W 0x0E8

0x20 Enable calibration factors (private)

W 0x152, Bits[1:0]

Configure the DAC decode mode (0b00 = NRZ, 0b01 = Mix-Mode, or 0b10 = RZ)

1 N/A means not applicable.

Table 44. Configure JESD204B Start-Up Sequence

R/W Register

Value Description

W 0x300

0x00 Ensure the SERDES links are disabled before configuring them.

W 0x4B8

0xFF Enable JESD204B interrupts.

W 0x4B9

0x01 Enable JESD204B interrupts.

W 0x480