AD9161 Datasheet, PDF (71/139 Pages) –

Data Sheet
AD9161/AD9162
INTERRUPT REQUEST OPERATION
The AD9161/AD9162 provide an interrupt request output
signal (IRQ) on Ball G1 (8 mm × 8 mm package) or Ball G4
(11 mm × 11 mm package) that can be used to notify an external
host processor of significant device events. On assertion of the
interrupt, query the device to determine the precise event that
occurred. The IRQ pin is an open-drain, active low output. Pull
the IRQ pin high, external to the device. This pin can be tied to
the interrupt pins of other devices with open-drain outputs to
wire; OR these pins together.
Figure 175 shows a simplified block diagram of how the IRQ
blocks works. If IRQ_EN is low, the INTERRUPT_SOURCE
signal is set to 0. If IRQ_EN is high, any rising edge of EVENT
causes the INTERRUPT_SOURCE signal to be set high. If any
INTERRUPT_SOURCE signal is high, the IRQ pin is pulled
low. INTERRUPT_SOURCE can be reset to 0 by either an
IRQ_RESET signal or a DEVICE_RESET signal.
Depending on the STATUS_MODE signal, the EVENT_STATUS
bit reads back an event signal or INTERRUPT_SOURCE signal.
The AD9161/AD9162 have several IRQ register blocks that can
monitor up to 75 events (depending on device configuration).
Certain details vary by IRQ register block as described in Table 40.
Table 41 shows the source registers of the IRQ_EN, IRQ_RESET,
and STATUS_MODE signals in Figure 175, as well as the address
where EVENT_STATUS is read back.
Table 40. IRQ Register Block Details
Register Block
Event
Reported
0x020, 0x024
Per chip
0x4B8 to 0x4BB; 0x470 Per link and
to 0x473
lane
EVENT_STATUS
INTERRUPT_SOURCE if
IRQ is enabled; if not, it
is the event signal
INTERRUPT_SOURCE if
IRQ is enabled; if not, 0
INTERRUPT SERVICE ROUTINE
Interrupt request management starts by selecting the set of event
flags that require host intervention or monitoring. Enable the
events that require host action so that the host is notified when
they occur. For events requiring host intervention upon IRQ
activation, run the following routine to clear an interrupt request:
1. Read the status of the event flag bits that are being monitored.
2. Disable the interrupt by writing 0 to IRQ_EN.
3. Read the event source.
4. Perform any actions that may be required to clear the cause
of the event. In many cases, no specific actions may be
required.
5. Verify that the event source is functioning as expected.
6. Clear the interrupt by writing 1 to IRQ_RESET.
7. Enable the interrupt by writing 1 to IRQ_EN.
0
EVENT_STATUS
1
STATUS_MODE
IRQ
IRQ_EN
0
INTERRUPT_SOURCE
EVENT
1
IRQ_EN
OTHER
INTERRUPT
SOURCES
IRQ_RESET
DEVICE_RESET
Figure 175. Simplified Schematic of IRQ Circuitry
Table 41. IRQ Register Block Address of IRQ Signal Details
Address of IRQ Signals
Register Block IRQ_EN
IRQ_RESET
STATUS_MODE¹
0x020, 0x024 0x020; R/W per chip
0x024; W per chip
STATUS_MODE = IRQ_EN
0x4B8 to 0x4BB 0x4B8, 0x4B9; W per error type 0x4BA, 0x4BB; W per error type N/A, STATUS_MODE = 1
0x470 to 0x473 0x470 to 0x473; W per error type 0x470 to 0x473; W per link
N/A, STATUS_MODE = 1
EVENT_STATUS
0x024; R per chip
0x4BA, 0x4BB; R per chip
0x470 to 0x473; R per link
1 _{N/A means not applicable.}
Rev. A | Page 71 of 139