ADSP-2185L Datasheet, PDF (8/31 Pages) Analog Devices – DSP Microcomputer

ADSP-2185L
Table II. Modes of Operations¹
MODE C² MODE B³ MODE A⁴ Booting Method
0
0
0
BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is configured
in Full Memory Mode.⁵
0
1
0
No Automatic boot operations occur. Program execution starts at external memory location
0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does
not automatically use or wait for these operations.
1
0
0
BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is config-
ured in Host Mode. (REQUIRES ADDITIONAL HARDWARE.)
1
0
1
IDMA feature is used to load any internal memory as desired. Program execution is held off
until internal program memory location 0 is written to. Chip is configured in Host Mode.⁵
NOTES
1_{All mode pins are recognized while RESET is active (low).}
2_{When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.}
3_{When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.}
4_{When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.}
5_{Considered as standard operating settings. Using these configurations allows for easier design and better memory management.}
MEMORY ARCHITECTURE
The ADSP-2185L provides a variety of memory and peripheral
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory, and I/O. Refer to the
following figures and tables for PM and DM memory alloca-
tions in the ADSP-2185L.
PROGRAM MEMORY
Program Memory (Full Memory Mode) is a 24-bit-wide
space for storing both instruction opcodes and data. The
ADSP-2185L has 16K words of Program Memory RAM on
chip, and the capability of accessing up to two 8K external
memory overlay spaces using the external data bus.
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16-bits wide only.
Table III. PMOVLAY Bits
PMOVLAY Memory A13
A12:0
0
Internal Not Applicable Not Applicable
1
External 0
Overlay 1
13 LSBs of Address
Between 0x2000
and 0x3FFF
2
External 1
Overlay 2
13 LSBs of Address
Between 0x2000
and 0x3FFF
PM (MODE B = 0)
PM (MODE B = 1)¹
INTERNAL
MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
ACCESSIBLE WHEN
PMOVLAY = 0
0x2000–
0x3FFF
0x2000–
0x3FFF²
ACCESSIBLE WHEN
PMOVLAY = 1
EXTERNAL _{ACCESSIBLE WHEN}
MEMORY
PMOVLAY = 2
0x2000–
0x3FFF²
INTERNAL
MEMORY
RESERVED
0x2000–
0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 0
0x0000–
0x1FFF²
ACCESSIBLE WHEN
PMOVLAY = 0
EXTERNAL
MEMORY
RESERVED
1_{WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0}
2_{SEE TABLE III FOR PMOVLAY BITS}
PROGRAM MEMORY
MODE B = 0 ADDRESS
0x3FFF
8K INTERNAL
PMOVLAY = 0
OR
8K EXTERNAL
PMOVLAY = 1 OR 2
0x2000
0x1FFF
8K INTERNAL
PROGRAM MEMORY
MODE B = 1 ADDRESS
0x3FFF
8K INTERNAL
PMOVLAY = 0
8K EXTERNAL
0x2000
0x1FFF
0x0000
Figure 4. Program Memory
0x0000
–8–
REV. A