AD9649 Datasheet, PDF (8/32 Pages) Analog Devices – 14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter

AD9649
TIMING SPECIFICATIONS
Table 5.
Parameter
Conditions
Min
Typ
Max Unit
SPI TIMING REQUIREMENTS
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
ns
tH
Hold time between CSB and SCLK
2
ns
tHIGH
SCLK pulse width high
10
ns
tLOW
SCLK pulse width low
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input to an
10
ns
output relative to the SCLK falling edge
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an
10
ns
input relative to the SCLK rising edge
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