AD9649 Datasheet, PDF (19/32 Pages) Analog Devices – 14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter

VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9649. The VREF can be configured using either the internal
1.0 V reference or an externally applied 1.0 V reference voltage.
The various reference modes are summarized in the sections
that follow. The Reference Decoupling section describes the
best practices PCB layout of the reference.
Internal Reference Connection
A comparator within the AD9649 detects the potential at the
SENSE pin and configures the reference into two possible modes,
which are summarized in Table 10. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 43), setting VREF to 1.0 V.
VIN+
VIN–
ADC
CORE
1.0µF
VREF
0.1µF
SENSE
SELECT
LOGIC
0.5V
ADC
Figure 43. Internal Reference Configuration
If the internal reference of the AD9649 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 44 shows
how the internal reference voltage is affected by loading.
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 45 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
AD9649
0
–0.5
–1.0
INTERNAL VREF = 0.996V
–1.5
–2.0
–2.5
–3.0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (mA)
Figure 44. VREF Accuracy vs. Load Current
4
3
2
VREF ERROR (mV)
1
0
–1
–2
–3
–4
–5
–6
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 45. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 28). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
Table 10. Reference Configuration Summary
Selected Mode
SENSE Voltage (V)
Fixed Internal Reference
AGND to 0.2
Fixed External Reference
AVDD
Resulting VREF (V)
1.0 internal
1.0 applied to external VREF pin
Resulting Differential Span (V p-p)
2.0
2.0
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