AD9522-2 Datasheet, PDF (8/84 Pages) Analog Devices – 12 LVDS/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO

AD9522-2
TIMING CHARACTERISTICS
Table 5.
Parameter
LVDS OUTPUT RISE/FALL TIMES
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUTPUT
For All Divide Values
Variation with Temperature
OUTPUT SKEW, LVDS OUTPUTS¹
LVDS Outputs That Share the Same Divider
LVDS Outputs on Different Dividers
All LVDS Outputs Across Multiple Parts
CMOS OUTPUT RISE/FALL TIMES
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT
For All Divide Values
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS¹
CMOS Outputs That Share the Same Divider
All CMOS Outputs on Different Dividers
All CMOS Outputs Across Multiple Parts
OUTPUT SKEW, LVDS-TO-CMOS OUTPUT¹
Outputs That Share the Same Divider
Outputs That Are on Different Dividers
Min Typ Max Unit Test Conditions/Comments
Termination = 100 Ω across differential pair
150 350 ps 20% to 80%, measured differentially
150 350 ps 80% to 20%, measured differentially
1866
1808
1913
2313
2245
1
7
19
625
625
2400
2
2812
2740
60
162
432
835
800
2950
ps
ps
ps/°C
ps
ps
ps
ps
ps
ps
ps/°C
High frequency clock distribution configuration
Clock distribution configuration
Termination = 100 Ω across differential pair
Termination = open
20% to 80%; CLOAD = 10 pF
80% to 20%; CLOAD = 10 pF
Clock distribution configuration
10 55 ps
27 230 ps
500 ps
−31 +152 +495 ps
−193 +160 +495 ps
All settings identical; different logic type
LVDS to CMOS on the same part
LVDS to CMOS on the same part
1 _{The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.}
Timing Diagrams
t_CLK
CLK
t_LVDS
t_CMOS
Figure 2. CLK/CLK to Clock Output Timing, DIV = 1
DIFFERENTIAL
80%
LVDS
20%
t_RP
t_FP
Figure 3. LVDS Timing, Differential
SINGLE-ENDED
80%
20%
CMOS
10pF LOAD
t_RC
t_FC
Figure 4. CMOS Timing, Single-Ended, 10 pF Load
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