AD9517-2_15 Datasheet, PDF (8/80 Pages) Analog Devices – 12-Output Clock Generator with Integrated 2.2 GHz VCO

AD9517-2
Data Sheet
TIMING CHARACTERISTICS
Table 5.
Parameter
Min
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT
High Frequency Clock Distribution Configuration 835
Clock Distribution Configuration
773
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS¹
LVPECL Outputs That Share the Same Divider
LVPECL Outputs on Different Dividers
All LVPECL Outputs Across Multiple Parts
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUTPUT
For All Divide Values
1.4
Variation with Temperature
OUTPUT SKEW, LVDS OUTPUTS¹
LVDS Outputs That Share the Same Divider
LVDS Outputs on Different Dividers
All LVDS Outputs Across Multiple Parts
CMOS
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT
For All Divide Values
1.6
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS¹
CMOS Outputs That Share the Same Divider
All CMOS Outputs on Different Dividers
All CMOS Outputs Across Multiple Parts
DELAY ADJUST³
Shortest Delay Range⁴
Zero Scale
50
Full Scale
540
Longest Delay Range⁴
Zero Scale
200
Quarter Scale
1.72
Full Scale
5.7
Delay Variation with Temperature
Short Delay Range⁵
Zero Scale
Full Scale
Long Delay Range⁵
Zero Scale
Full Scale
Typ Max Unit Test Conditions/Comments
Termination = 50 Ω to VS − 2 V; level = 810 mV
70
180 ps
20% to 80%, measured differentially
70
180 ps
80% to 20%, measured differentially
995 1180 ps
See Figure 43
933 1090 ps
See Figure 45
0.8
ps/°C
5
15 ps
13 40 ps
220 ps
Termination = 100 Ω differential; 3.5 mA
170 350 ps
20% to 80%, measured differentially²
160 350 ps
20% to 80%, measured differentially²
Delay off on all outputs
1.8 2.1 ns
1.25
ps/°C
Delay off on all outputs
6
62 ps
25 150 ps
430 ps
Termination = open
495 1000 ps
20% to 80%; CLOAD = 10 pF
475 985 ps
80% to 20%; CLOAD = 10 pF
Fine delay off
2.1 2.6 ns
2.6
ps/°C
Fine delay off
4
66 ps
28 180 ps
675 ps
LVDS and CMOS
Register 0x0A1 (0x0A4, 0x0A7, 0x0AA), Bits[5:0] = 101111b
315 680 ps
Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b
880 1180 ps
Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b
Register 0x0A1 (0x0A4, 0x0A7, 0x0AA), Bits[5:0] = 000000b
570 950 ps
Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b
2.31 2.89 ns
Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 001100b
8.0 10.1 ns
Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b
0.23
−0.02
0.3
0.24
ps/°C
ps/°C
ps/°C
ps/°C
1 _{This is the difference between any two similar delay paths while operating at the same voltage and temperature.}
2 _{Corresponding CMOS drivers set to A for noninverting and B for inverting.}
3 _{The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.}
4 _{Incremental delay; does not include propagation delay.}
5 _{All delays between zero scale and full scale can be estimated by linear interpolation.}
Rev. E | Page 8 of 80