AD9430_10 Datasheet, PDF (8/44 Pages) Analog Devices – 12-Bit, 170/210 MSPS 3.3 V A/D Converter

AD9430
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 4.
Parameter (Conditions)
Maximum Conversion Rate¹
Minimum Conversion Rate¹
CLK+ Pulse Width High (tEH)¹
CLK+ Pulse Width Low (tEL)¹
DS Input Setup Time (tSDS)²
DS Input Hold Time (tHDS)²
OUTPUT (CMOS Mode)
Valid Time (tV)
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tPD to tCPD)
Interleaved Mode (A, B Latency)
Parallel Mode (A, B Latency)
OUTPUT (LVDS Mode)
Valid Time (tV)
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tPD – tCPD)
Latency
APERTURE DELAY (tA)
APERTURE UNCERTAINTY (Jitter, tJ)
OUT OF RANGE RECOVERY TIME (CMOS and LVDS)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
25°C
25°C
25°C
1 _{All ac specifications tested by differentially driving CLK+ and CLK−.}
2 _{DS inputs used in CMOS mode only.}
Test
Level
VI
V
IV
IV
IV
IV
IV
IV
V
V
IV
IV
IV
IV
VI
VI
V
V
VI
IV
IV
V
V
V
AD9430-170
Min Typ
Max
170
40
2
12.5
2
12.5
–0.5
1.75
2
3.8
5
1
1
3.8
5
–0.5 0
+0.5
14, 14
15, 14
2.0
3.2
4.3
0.5
0.5
1.8 2.7
3.8
0.2 0.5
0.8
14
1.2
0.25
1
AD9430-210
Min Typ Max
210
40
2
12.5
2
12.5
–0.5
1.75
Unit
MSPS
MSPS
ns
ns
ns
ns
2
ns
3.8
5
ns
1
ns
1
ns
3.8
5
ns
–0.5 0
+0.5 ns
14, 14
Cycles
15, 14
Cycles
2.0
3.2
0.5
0.5
1.8 2.7
0.2 0.5
14
1.2
0.25
ns
4.3 ns
ns
ns
3.8 ns
0.8 ns
Cycles
ns
ps rms
1
Cycles
Rev. E | Page 8 of 44