AD9430_10 Datasheet, PDF (14/44 Pages) Analog Devices – 12-Bit, 170/210 MSPS 3.3 V A/D Converter

AD9430
Pin Number
22
32
36
37
47, 54, 62, 75, 83
48, 53, 61, 67, 74, 82
49
50
51
52
55
56
57
58
59
60
63
64
65
66
68
69
70
71
72
73
76
77
78
79
80
81
84
85
Mnemonic
VIN–
GND
CLK+
CLK–
DRVDD
DRGND¹
D0–
D0+
D1–
D1+
D2–
D2+
D3–
D3+
D4–
D4+
DCO–
DCO+
D5–
D5+
D6–
D6+
D7–
D7+
D8–
D8+
D9–
D9+
D10–
D10+
D11–
D11+
OR–
OR+
Description
Analog Input—Complement.
Data Sync (Input)—Not Used in LVDS Mode. Tie to GND.
Clock Input—True (LVPECL Levels).
Clock Input—Complement (LVPECL Levels).
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Digital Output Ground.
D0 Complement Output Bit (LSB).
D0 True Output Bit (LSB).
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
Data Clock Output—Complement.
Data Clock Output—True.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
Overrange Complement Output Bit.
Overrange True Output Bit.
1 _{AGND and DRGND should be tied together to a common ground plane.}
2 _{Pin 33 can be tied to AVDD (as recommended) or left floating with no ill effects}
Rev. E | Page 14 of 44