AD7654_15 Datasheet, PDF (8/27 Pages) Analog Devices – 16-Bit, 500 kSPS PulSAR Dual, 2-Channel, Simultaneous Sampling ADC

AD7654
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
AGND 1
AVDD 2
A0 3
BYTESWAP 4
A/B 5
DGND 6
IMPULSE 7
SER/PAR 8
D0 9
D1 10
D2/DIVSCLK[0] 11
D3/DIVSCLK[1] 12
PIN 1
AD7654
TOP VIEW
(Not to Scale)
36 DVDD
35 CNVST
34 PD
33 RESET
32 CS
31 RD
30 EOC
29 BUSY
28 D15
27 D14
26 D13
25 D12
13 14 15 16 17 18 19 20 21 22 23 24
AGND 1
AVDD 2
A0 3
BYTESWAP 4
A/B 5
DGND 6
IMPULSE 7
SER/PAR 8
D0 9
D1 10
D2/DIVSCLK[0] 11
D3/DIVSCLK[1] 12
Data Sheet
AD7654
TOP VIEW
(Not to Scale)
36 DVDD
35 CNVST
34 PD
33 RESET
32 CS
31 RD
30 EOC
29 BUSY
28 D15
27 D14
26 D13
25 D12
Figure 4. 48-Lead LQFP (ST-48) Pin Configuration
NOTES
1. THE EPAD IS CONNECTED TO GROUND; HOWEVER, THIS CONNECTION
IS NOT REQUIRED TO MEET SPECIFIED PERFORMANCE.
Figure 5. 48-Lead LFCSP (CP-48) Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type¹ Description
1, 47, 48 AGND
P
Analog Power Ground Pin.
2
AVDD
P
Input Analog Power Pin. Nominally 5 V.
3
A0
DI
Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously, then
converted. When HIGH, the analog inputs INA2 and INB2 are sampled simultaneously, then converted.
4
BYTESWAP DI
Parallel Mode Selection (8 bit, 16 bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5
A/B
DI
Data Channel Selection. In parallel mode, when LOW, the data from Channel B is read. When HIGH, the
data from Channel A is read. In serial mode, when HIGH, Channel A is output first followed by Channel
B. When LOW, Channel B is output first followed by Channel A.
6, 20
DGND
P
Digital Power Ground.
7
IMPULSE
DI
Mode Selection. When HIGH, this input selects a reduced power mode. In this mode, the power
dissipation is approximately proportional to the sampling rate.
8
SER/PAR
DI
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface
mode is selected and some bits of the DATA bus are used as a serial port.
9, 10
D[0:1]
DO
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high
impedance.
11, 12 D[2:3] or
DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
DIVSCLK[0:1]
When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW, which is the serial master read after
convert mode, these inputs, part of the serial port, are used to slow down if desired the internal serial
clock that clocks the data output. In the other serial modes, these inputs are not used.
13
D[4]
DI/O When SER/PARis LOW, this output is used as Bit 4 of the parallel port data output bus.
or EXT/INT
When SER/PARis HIGH, this input, part of the serial port, is used as a digital select input for choosing
the internal or an external data clock, called respectively, master and slave mode. With EXT/INT tied
LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is
synchronized to an external clock signal connected to the SCLK input.
14
D[5]
DI/O When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus.
or INVSYNC
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal in Master modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
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