AD5755_11 Datasheet, PDF (8/48 Pages) Analog Devices – Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA and Voltage Output DAC, Dynamic Power Control

AD5755
Parameter¹
Current Output
Output Current Settling Time
Output Noise (0.1 Hz to 10 Hz
Bandwidth)
Output Noise Spectral Density
Min Typ
Max
15
See test conditions/
comments
0.15
0.5
1 _{Guaranteed by design and characterization; not production tested.}
Unit Test Conditions/Comments
μs
To 0.1% FSR (0 mA to 24 mA)
ms
See Figure 48, Figure 49, and Figure 50
LSB p-p 16-bit LSB, 0 mA to 24 mA range
nA/√Hz Measured at 10 kHz, midscale output, 0 mA to
24 mA range
TIMING CHARACTERISTICS
AVDD = VBOOST_x = 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =
GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications TMIN to TMAX, unless
otherwise noted.
Table 3.
Parameter^{1, 2, 3}
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19 ⁴
Limit at TMIN, TMAX
33
13
13
13
13
198
5
5
20
5
10
500
See the AC Performance
Characteristics section
10
5
40
21
5
500
800
20
5
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs min
μs min
ns min
ns max
μs max
ns min
μs max
ns max
μs min
μs min
ns min
ns min
μs min
μs min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24^th/32^nd SCLK falling edge to SYNC rising edge (see Figure 77)
SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated or any channel has
digital slew rate control enabled)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLEAR high time
CLEAR activation time
SCLK rising edge to SDO valid
SYNC rising edge to DAC output response time (LDAC = 0) (all DACs updated)
SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated)
LDAC falling edge to SYNC rising edge
RESET pulse width
SYNC high to next SYNC low (digital slew rate control enabled) (all DACs updated)
SYNC high to next SYNC low (digital slew rate control disabled) (single DAC
updated)
1 _{Guaranteed by design and characterization; not production tested.}
2 _{All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.}
3 _{See Figure 3, Figure 4, Figure 5, and Figure 6.}
4 _{This specification applies if LDAC is held low during the write cycle; otherwise, see t9.}
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