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5962-9756401QXA Datasheet, PDF (8/16 Pages) Analog Devices – 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters
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AD976/AD976A
CONVERSION CONTROL
The AD976/AD976A is controlled by two signals: R/C and CS,
as shown in Figures 2 and 3. To initiate a conversion and place
the sample/hold circuit into the hold state, both the R/C and CS
signals must be brought low for no less than 50 ns. Once the
conversion process begins, the BUSY signal will go Low until
the conversion is complete. At the end of a conversion, BUSY
will return High, and the resulting valid data will be available on
the data bus. On the first conversion after the AD976/AD976A
is powered up, the DATA output will be indeterminate.
The AD976/AD976A exhibits two modes of conversion. In the
mode demonstrated in Figure 2, conversion timing is controlled
by a negative-going R/C signal, at least 50 ns wide. In this mode
the CS pin is always tied low, and the only limit placed on how
long the R/C signal can remain low is the desired sampling rate.
Less than 83 ns after the initiation of a conversion, the BUSY
signal will be brought low and remain low until the conversion is
complete and the output shift registers have been updated with
the new Binary Twos Complement data.
Figure 3 demonstrates the AD976/AD976A conversion timing,
using CS to control both the conversion process and the reading
of output data. To operate in this mode, the R/C signal should
be brought low no less than 10 ns before the falling edge of a CS
pulse (50 ns wide) is applied to the ADC. Once these two pulses
are applied, BUSY will go low and remain low until a conver-
sion is complete. After a maximum of 4 µs (AD976A only),
BUSY will again return high, and parallel data will be valid on
the ADC outputs. To achieve the maximum 100 kHz/200 kHz
throughput rate of the part, the negative going R/C and CS
control signals should be applied every 5 µs (AD976A). It should
also be noted that although all R/C and CS commands will be
ignored once a conversion has begun, these inputs can be
asserted during a conversion; i.e., a read during conversion can
be performed. Voltage transients on these inputs could feed
through to the analog circuitry and affect conversion results.
t1
R/C
BUSY
MODE
ACQUIRE
t3
t6
t13
t2
t4
CONVERT
t5
ACQUIRE
CONVERT
t7
t8
DATA
BUS
PREVIOUS
DATA VALID
HI-Z
PREVIOUS
DATA VALID
NOT
VALID
DATA
VALID
HI-Z
t9
t14
t10
t11
DATA
VALID
Figure 2. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low)
R/C
CS
BUSY
MODE
DATA
BUS
t12
t 12
t 12
t 12
t1
t1
t3
t4
t6
ACQUIRE
CONVERT
ACQUIRE
t7
HI-Z
HI-Z
DATA VALID
t14
t9
Figure 3. Using CS to Control Conversion and Read Timing
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REV. C
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