ADV7392_15 Datasheet, PDF (79/108 Pages) Analog Devices – Low Power, Chip Scale, 10-Bit SD/HD Video Encoder

Data Sheet
INTERNAL TEST PATTERN GENERATION
SD TEST PATTERNS
The ADV739x is able to internally generate SD color bar and
black bar test patterns. For this function, a 27 MHz clock signal
must be applied to the CLKIN pin.
The register settings in Table 60 are used to generate an SD NTSC
75% color bar test pattern. All other registers are set as normal/
default. Component YPrPb output is available on DAC 1 to
DAC 3. On power-up, the subcarrier frequency registers default
to the appropriate values for NTSC.
Table 60. SD NTSC Color Bar Test Pattern Register Writes
Subaddress
Setting
0x00
0x1C
0x82
0xC9
0x84
0x40
For CVBS and S-Video (Y/C) output, 0xCB instead of 0xC9
should be written to Subaddress 0x82.
For component RGB output rather than YPrPb output, 0 should
be written to Subaddress 0x02, Bit 5.
To generate an SD NTSC black bar test pattern, the settings
shown in Table 60 should be used with an additional write of
0x24 to Subaddress 0x02.
For PAL output of either test pattern, the same settings are used
except that Subaddress 0x80 is programmed to 0x11, and the
subcarrier frequency (FSC) registers are programmed as shown
in Table 61.
Table 61. PAL FSC Register Writes
Subaddress
Description
0x8C
FSC0
0x8D
FSC1
0x8E
FSC2
0x8F
FSC3
Setting
0xCB
0x8A
0x09
0x2A
Note that, when programming the FSC registers, the user must
write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full
FSC value to be written is only accepted after the FSC3 write is
complete.
ADV7390/ADV7391/ADV7392/ADV7393
ED/HD TEST PATTERNS
The ADV739x is able to internally generate ED/HD color bar,
black bar, and hatch test patterns. For ED test patterns, a 27 MHz
clock signal must be applied to the CLKIN pin. For HD test
patterns, a 74.25 MHz clock signal must be applied to the
CLKIN pin.
The register settings in Table 62 are used to generate an ED
525p hatch test pattern. All other registers are set as normal/
default. Component YPrPb output is available on DAC 1 to
DAC 3. For component RGB output rather than YPrPb output,
0 should be written to Subaddress 0x02, Bit 5.
Table 62. ED 525p Hatch Test Pattern Register Writes
Subaddress
Setting
0x00
0x1C
0x01
0x10
0x31
0x05
To generate an ED 525p black bar test pattern, the settings
shown in Table 62 should be used with an additional write of
0x24 to Subaddress 0x02.
To generate an ED 525p flat field test pattern, the settings
shown in Table 62 should be used, except that 0x0D should be
written to Subaddress 0x31.
The Y, Cr, and Cb levels for the hatch and flat field test patterns
can be controlled using Subaddress 0x36, Subaddress 0x37, and
Subaddress 0x38, respectively.
For ED/HD standards other than 525p, the settings shown in
Table 62 (and subsequent comments) are used, except that
Subaddress 0x30, Bits[7:3] are updated as appropriate.
Rev. H | Page 79 of 108