ADUC847_15 Datasheet, PDF (79/108 Pages) Analog Devices – 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU

Data Sheet
ADuC845/ADuC847/ADuC848
Timer/Counter 2 Operating Modes
The following sections describe the operating modes for
Timer/Counter 2. The operating modes are selected by bits in
the T2CON SFR as shown in Table 53.
Table 53. T2CON Operating Modes
RCLK (or) TCLK
CAP2 TR2
0
0
1
0
1
1
1
X
1
X
X
0
Mode
16-Bit Autoreload
16-Bit Capture
Baud Rate
Off
16-Bit Autoreload Mode
Autoreload mode has two options that are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, when Timer 2 rolls over, it
not only sets TF2 but also causes the Timer 2 registers to be
reloaded with the 16-bit value in registers RCAP2L and
RCAP2H, which are preset by software. If EXEN2 = 1, Timer 2
still performs the above, but with the added feature that a 1-to-0
transition at external input T2EX also triggers the 16-bit reload
and sets EXF2. Autoreload mode is shown in Figure 56.
16-Bit Capture Mode
Capture mode has two options that are selected by Bit EXEN2
in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter
that, upon overflowing, sets bit TF2, the Timer 2 overflow bit,
which can be used to generate an interrupt. If EXEN2 = 1,
Timer 2 still performs the above, but a l-to-0 transition on
external input T2EX causes the current value in the Timer 2
registers, TL2 and TH2, to be captured into Registers RCAP2L
and RCAP2H, respectively. In addition, the transition at T2EX
causes Bit EXF2 in T2CON to be set, and EXF2, like TF2, can
generate an interrupt. Capture mode is shown in Figure 57. The
baud rate generator mode is selected by RCLK = 1 and/or
TCLK = 1.
In either case, if Timer 2 is used to generate the baud rate, the
TF2 interrupt flag does not occur. Therefore, Timer 2 interrupts
do not occur, so they do not have to be disabled. In this mode,
the EXF2 flag can, however, still cause interrupts, which can be
used as a third external interrupt. Baud rate generation is
described as part of the UART serial port operation in the
following section.
CORE
CLK¹
T2
PIN
C/ T2 = 0
C/ T2 = 1
TL2
(8 BITS)
TH2
(8 BITS)
CONTROL
TRANSITION
DETECTOR
T2EX
PIN
TR2
RELOAD
RCAP2L RCAP2H
TF2
EXF2
TIMER
INTERRUPT
CONTROL
EXEN2
*NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 56. Timer/Counter 2, 16-Bit Autoreload Mode
CORE
CLK¹
T2
PIN
C/ T2 = 0
TL2
TH2
(8 BITS) (8 BITS)
TF2
C/ T2 = 1
CONTROL
TRANSITION
DETECTOR
TR2
CAPTURE
RCAP2L RCAP2H
TIMER
INTERRUPT
T2EX
PIN
CONTROL
EXEN2
*NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
EXF2
Figure 57. Timer/Counter 2, 16-Bit Capture Mode
Rev. C | Page 79 of 108