AD6636_15 Datasheet, PDF (77/80 Pages) Analog Devices – 150 MSPS, Wideband, Digital Downconverter

DESIGN NOTES
The following guidelines describe circuit connections, layout
requirements, and programming procedures for the AD6636.
The designer should review these guidelines before starting the
system design and layout.
• The AD6636 requires the following power-up sequence. The
VDDCORE (1.8 V) must settle into nominal voltage levels
before the VDDIO attains the minimum. This ensures that,
on power-up, the JTAG does not take control of the I/O pins.
• Input clocks (CLKA, CLKB, CLKC, CLKD) and input port
pins (INA[15:0] to IND[15:0], EXPA[2:0] to EXPD[2:0]) are
not 5 V tolerant. Care should be taken to drive these pins
within the limits of VDDIO (3.0 V to 3.6 V).
• When the ADC output has less than 16 bits of resolution,
it should be connected to the MSBs of the input port (MSB-
justified). The remaining LSBs should be connected to
ground.
• The number format used in this part is twos complement. All
input ports and output ports use twos complement data
format. The formats for individual internal registers are given
in the memory map description of these registers.
• In both microport and serial port operation, the DTACK
(RDY, SDO) pin is an open-drain output and therefore
should be pulled high externally using a pull-up resister.
The recommended value for the pull-up resistor is from
1 kΩ to 5 kΩ.
3.3V
1kΩ
DTACK (RDY, SDO)
AD6636
Figure 58. DTACK, SDO Pull-Up Resistor Circuit
• A simple RC circuit is used on the EXT_FILTER pin to
balance the internal RC circuit on this pin and maintain a
good PLL clock lock. The recommended circuit is shown in
Figure 59, with the RC circuit connected to VDDCORE. This
RC circuit should be placed as close as possible to the
AD6636 part. This layout ensures that the PLL clock is void
of noise and spurs and the PLL lock is maintained closely.
AD6636
VDDCORE (1.8V)
0.01μF
250Ω
EXT_FILTER
AD6636
Figure 59. EXT_FILTER Circuit for PLL Clock
• By default, the PLL CLK is disabled. It can be enabled by
programming the PLL multiplier and divider bits in the ADC
CLK control register. When the PLL CLK is enabled by
programming this register, it takes between 50 μs and 200 μs
to settle. While the PLL loop settles, the voltage at the
EXT_FILTER pin increases from 0 V to VDDCORE (1.8 V)
and settles there. Channel registers and output port registers
(Address 0x68 to Address 0xE7) should not be programmed
before the PLL loop settles.
• The LVDS_RSET pin is used to calibrate the current in the
LVDS pads. The recommended circuit for this pin is shown
in Figure 60. This resistor should be placed as close as
possible to the AD6636 part. If CMOS mode input is used,
this resistor is not required.
10kΩ
LVDS_RSET
AD6636
Figure 60. LVDS_RSET Circuit for LVDS Calibration
• To reset the AD6636 part, the user needs to provide a
minimum pulse of 30 ns to the RESET pin. The RESET pin
should be connected to GND (or pulled low) during power-
up of the part. The RESET pin can be pulled high after the
power supplies have settled to nominal values (1.8 V and
3.3 V). At this point, a pulse (pull low and high again) should
be provided to give a RESET to the part.
• Most AD6636 pins are driven by both JTAG circuitry and
normal function circuitry specific to each pin. TRST is the
reset pin for JTAG. When TRST is pulled low, JTAG is in
reset and all pins function in normal mode (driven by the
functional circuit). If JTAG is not used in the design, the
TRST pin should be pulled low at all times.
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