AD6636_15 Datasheet, PDF (52/80 Pages) Analog Devices – 150 MSPS, Wideband, Digital Downconverter

AD6636
SPI Mode Timing
In SPI mode, the SCLK should run only when data is being
transferred and SCS is logic low. If SCLK runs when SCS is logic
high, the internal shift register continues to run and instruction
words or data are lost. No external framing is necessary. The
SCS pin can be pulled low once for each byte of transfer, or kept
low for the whole length of the transfer.
SPI Write
Data on the SDI pin is registered on the rising edge of SCLK.
During a write, the serial port accumulates eight input bits
of data before transferring one byte to the internal registers.
Figure 48 and Figure 49 show one byte block transfer for
writing in MSB_FIRST and LSB_FIRST modes.
MSBFIRST
SCLK
SCS
SMODE
SDI
SDO
MODE
MSBFIRST
SCLK
SCS
SMODE
SDI
SDO
MODE
BLOCK END ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
WRITE
BLOCK COUNT (Nx)
0 N6 N5 N4 N3 N2 N1 N0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 48. SPI Write MSB_FIRST = 1
BLOCK END ADDRESS
A0 A1 A2 A3 A4 A5 A6 A7
BLOCK COUNT (Nx)
WRITE
N0 N1 N2 N3 N4 N5 N6 0
D0 D1 D2 D3 D4 D5 D6 D7
Figure 49. SPI Write MSB_FIRST = 0
Rev. A | Page 52 of 80