ADT7490_15 Datasheet, PDF (74/76 Pages) Analog Devices – dBCool Remote Thermal Monitor and Fan Controller with PECI Interface

ADT7490
Table 88. Register 0x8F—Dynamic TMIN Control Register 2 (Power-On Default = 0x00)
Bit No. Mnemonic R/W¹
Description
[2:0] CYR1
R/W
3-Bit Remote 1 Cycle Value. These three bits define the delay time between making subsequent TMIN
adjustments in the control loop for the Remote 1 channel in terms of number of monitoring cycles.
The system has associated thermal time constants that need to be found to optimize the response of
fans and the control loop.
Bit Code
Decrease Cycle
Increase Cycle
000
8 cycles (1 sec)
16 cycles (2 sec)
001
16 cycles (2 sec)
32 cycles (4 sec)
010
32 cycles (4 sec)
64 cycles (8 sec)
011
64 cycles (8 sec)
128 cycles (16 sec)
100
128 cycles (16 sec)
256 cycles (32 sec)
101
256 cycles (32 sec)
512 cycles (64 sec)
110
512 cycles (64 sec)
1024 cycles (128 sec)
111
1024 cycles (128 sec) 2048 cycles (256 sec)
[5:3] CYL
R/W
3-Bit Local Temperature Cycle Value. These three bits define the delay time between making
subsequent TMIN adjustments in the control loop for the local temperature channel in terms of
number of monitoring cycles. The system has associated thermal time constants that need to be
found to optimize the response of fans and the control loop.
Bit Code
Decrease Cycle
Increase Cycle
000
8 cycles (1 sec)
16 cycles (2 sec)
001
16 cycles (2 sec)
32 cycles (4 sec)
010
32 cycles (4 sec)
64 cycles (8 sec)
011
64 cycles (8 sec)
128 cycles (16 sec)
100
128 cycles (16 sec)
256 cycles (32 sec)
101
256 cycles (32 sec)
512 cycles (64 sec)
110
512 cycles (64 sec)
1024 cycles (128 sec)
111
1024 cycles (128 sec) 2048 cycles (256 sec)
[7:6] CYR2
R/W
2 LSBs of 3-Bit Remote 2 Cycle Value. The MSB of the 3-bit code resides in the Dynamic TMIN Control
Register 1 (Register 0x8E). These three bits define the delay time between making subsequent TMIN
adjustments in the control loop for the Remote 2 channel in terms of number of monitoring cycles.
The system has associated thermal time constants that need to be found to optimize the response of
fans and the control loop.
Bit Code
Decrease Cycle
Increase Cycle
000
8 cycles (1 sec)
16 cycles (2 sec)
001
16 cycles (2 sec)
32 cycles (4 sec)
010
32 cycles (4 sec)
64 cycles (8 sec)
011
64 cycles (8 sec)
128 cycles (16 sec)
100
128 cycles (16 sec)
256 cycles (32 sec)
101
256 cycles (32 sec)
512 cycles (64 sec)
110
512 cycles (64 sec)
1024 cycles (128 sec)
111
1024 cycles (128 sec) 2048 cycles (256 sec)
1 _{This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail.}
Rev. 0 | Page 74 of 76