ADT7490_15 Datasheet, PDF (54/76 Pages) Analog Devices – dBCool Remote Thermal Monitor and Fan Controller with PECI Interface

ADT7490
Table 36. Register 0x36—PECI Configuration Register 1 (Power-On Default = 0x00)
Bit No. Mnemonic R/W¹ Description
[2:0] AVG
R/W PECI Smoothing Interval. These bit set the duration over which smoothing is carried out on the PECI data
read. Note that the PECI smoothing interval is equal to the PECI register update interval.
The smoothing interval is calculated using the following formula:
Smoothing Interval = # reads × (t _BIT × 67 × # CPU + t _IDLE )
where:
#reads is the number of readings defined below.
tBIT is the negotiated bit rate.
67 is the number of bits in each PECI reading.
#CPU is the number of CPUs providing PECI data (1 to 4).
tIDLE = 14 μs, the delay between consecutive reads.
Bit Code
Number of PECI readings
000
16
001
2048
010
4096
011
8192
100
16384
101
32768
110
65536
111
Reserved
[3]
DOM0
R/W CPU Domain Count information. Set to 0 indicates that CPU 1 associated with the PECI0 reading has a
single domain (default). Set to 1 indicates that the system CPU 1 contains two domains.
[4]
REPLACE R/W If this bit is set to 0, it indicates that the ADT7490 is operating in standard mode. If this bit is set to 1, the
Remote 1 Temperaute register (Register 0x25) is overwritten by PECI0 information (Register 0x33) and vice
versa. Note that in this mode, all associated user programmable limit and fan control registers are also
swapped and should be programmed in the appropriate PECI or absolute temperature format.
[7:5] RES
R
Reserved.
1 _{These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.}
Table 37. Maximum PWM Duty Cycle (Power-On Default = 0xFF)¹
Register Address
R/W²
Description
0x38
R/W
Maximum duty cycle for PWM1 output, default = 100% (0xFF).
0x39
R/W
Maximum duty cycle for PWM2 output, default = 100% (0xFF).
0x3A
R/W
Maximum duty cycle for PWM3 output, default = 100% (0xFF).
1 _{These registers set the maximum PWM duty cycle of the PWM output.}
2 _{These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.}
Table 38. PECI TMIN Register (Power-On Default = 0xE0,Value = −32)
Register Address R/W¹
Description
0x3B
R/W
PECI TMIN. When the PECI measurement exceeds PECI TMIN, the appropriate fans run at PWMMIN and
increase according to the automatic fan speed control slope.
1 _{This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set. Any further attempts to write to this register have no effect.}
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