ADSP-BF522_15 Datasheet, PDF (72/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
JTAG Test And Emulation Port Timing
Table 64 and Figure 42 describe JTAG port operations.
Table 64. JTAG Port Timing
V_DDEXT
1.8V Nominal
V_DDEXT
2.5 V or 3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
t_TCK
TCK Period
20
20
ns
t_STAP
TDI, TMS Setup Before TCK High
4
4
ns
t_HTAP
TDI, TMS Hold After TCK High
4
4
ns
t_SSYS
System Inputs Setup Before TCK High¹
12
12
ns
t_HSYS
System Inputs Hold After TCK High¹
5
5
ns
t_TRSTW
TRST Pulse Width² (measured in TCK cycles)
4
4
TCK
Switching Characteristics
t_DTDO
t_DSYS
TDO Delay from TCK Low
System Outputs Delay After TCK Low³
10
10
ns
12
12
ns
1 _{System Inputs = DATA15–0, ARDY, SCL, SDA, PF15–0, PG15–0, PH15–0, RESET, NMI, BMODE3–0.}
2 _{50 MHz Maximum.}
3 _{System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, PF15–0, PG15–0, PH15–0.}
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t_TCK
t_STAP
t_DTDO
t_DSYS
t_SSYS
t_HTAP
t_HSYS
Figure 42. JTAG Port Timing
Rev. D | Page 72 of 88 | July 2013