ADSP-BF522_15 Datasheet, PDF (69/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Table 60. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Parameter¹
V_DDEXT
1.8V Nominal
Min
Max
V_DDEXT
2.5 V or 3.3V Nominal
Min
Max
Unit
Timing Requirements
t_EREFCLKF
t_EREFCLKW
t_EREFCLKIS
REF_CLK Frequency (f_SCLK = SCLK Frequency)
EREF_CLK Width (t_EREFCLK = EREFCLK Period)
Rx Input Valid to RMII REF_CLK Rising Edge (Data In
Setup)
None
50 + 1%
None
50 + 1%
MHz
t_EREFCLK × 40% t_EREFCLK × 60% t_EREFCLK × 35% t_EREFCLK × 65% ns
4
4
ns
t_EREFCLKIH
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In 2
2
ns
Hold)
1 _{RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.}
RMII_REF_CLK
t_REFCLKW
t_REFCLK
ERxD1–0
ERxDV
ERxER
t_REFCLKIS t_REFCLKIH
Figure 38. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Table 61. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
ADSP-BF522/ADSP-BF524/
ADSP-BF526
Parameter¹
V_DDEXT
1.8V Nominal
V_DDEXT
2.5 V or 3.3V
Nominal
Min Max Min
Max
Switching Characteristics
t_EREFCLKOV
RMII REF_CLK Rising Edge
8.1
8.1
to Tx Output Valid (Data Out Valid)
t_EREFCLKOH
RMII REF_CLK Rising Edge
2
2
to Tx Output Invalid (Data Out Hold)
1 _{RMII outputs synchronous to RMII REF_CLK are ETxD1–0.}
ADSP-BF523/ADSP-BF525/
ADSP-BF527
V_DDEXT
1.8V Nominal
V_DDEXT
2.5 V or 3.3V
Nominal
Min Max Min
Max
7.5
7.5
2
2
Unit
ns
ns
RMII_REF_CLK
ETxD1–0
ETxEN
t_REFCLK
t_REFCLKOH
t_REFCLKOV
Figure 39. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Rev. D | Page 69 of 88 | July 2013